• 제목/요약/키워드: Capacitance of Coupled Lines

검색결과 15건 처리시간 0.018초

MIC를 위한 2선 및 3선 결합선로의 Quasi TEM Mode 정수계산

  • 류범;김청식;진년강
    • 한국통신학회:학술대회논문집
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    • 한국통신학회 1986년도 춘계학술발표회 논문집
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    • pp.194-197
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    • 1986
  • The normal mode parameters of microstrip coupled lines are datermined from the self and mutual capacitance and inductance of microstrip lines. In this paper, these capacitance are computed by using the relaxation method based on Quas1-TEM model for shoelded structure. Using these results, the normal mode parameters of two and three microstrip coupled lines are obtained.

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쉬해석에 의한 다층 다중 결합 마이크로스트립 선로 해석 (Numerical Analysis of Multi-Layer Multi-Coupled Microstrip Lines)

  • 서철헌
    • The Journal of the Acoustical Society of Korea
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    • 제13권1E호
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    • pp.5-10
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    • 1994
  • 삼층 기판위의 삼중 결합 마이크로스트립 서로의 해석을 위한 수치해석의 일반식이 얻어졌다. 유한차분식을 얻기 위한 방법과 특이점 처리를 위한 최적의 방법이 구해졌다. 홀수 모드와 짝수 모드의 캐패시턴스와 특성 임피이던스의 수치해석 결과를 보였으며 그 결과들은 이층의 두께와 삼층의 마치크로스트립 폭의 비에 따라 구해졌다. 수치해석으로 구한 짝수 모드 캐패시턴스는 다른 수치해석 결과와 비교되었다.

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유한요소해석을 이용한 비대칭 평면형 결합선로 설계 (Design of Asymmetrical Parallel Coupled lines Using Finite Element Analysis)

  • 윤재호;박준석;안달;김형석
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 하계학술대회 논문집 C
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    • pp.1841-1843
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    • 2001
  • Asymmetrical parallel coupled lines are used in a number of circuits such as multi-band coupler and combline type band pass filter. Although graphical results and formulas are available for the design of coupled lines, the design procedure is hard to use, because even- and odd- mode impedances are always expressed in terms of the physical geometry. In this paper, we introduce a method to find design parameter using finite element analysis. By employing the capacitance obtained by FE analysis, design parameters for each lines are extracted. To show the validity of extracted design parameter for asymmetrical parallel coupled line, we have designed and simulated a planar type combline band pass filter.

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유한요소해석을 이용한 배열구조의 평면형 비대칭 결합선로 설계 (Design of Asymmetric Parallel Coupled-line Array using Finite Element Analysis)

  • 윤재호;박준석;김형석
    • 한국전자파학회논문지
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    • 제13권6호
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    • pp.521-527
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    • 2002
  • 본 논문에서는 배열구조의 비대칭 결합선로를 유한요소해석을 이용해서 설계하는 방법을 제시하였다. 비대칭 결합선로가 배열되어 있는 구조를 설계하기 위해 결합선로에서 나타나는 커패시턴스의 분포를 통해 설계에 필요한 몇 가지 설계법칙을 정의하였다. 제시한 배열구조의 비대칭 결합선로의 설계방법을 검증하기 위해 이동 통신 수동소자로 비대칭 결합선로의 배열구조로 되어 있는 comb-Line 대역통과여파기를 직접 설계, 측정하여 설계방법의 타당성을 확인하였다.

Compact CMOS C-Band Bandpass Filter Using lnterdigital Capacitor

  • Kang, In-Ho;Wang, Xu-Guang
    • 한국항해항만학회지
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    • 제31권9호
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    • pp.759-762
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    • 2007
  • A novel miniaturized CMOS C-Band bandpass filter based on diagonally end-shorted coupled lines and interdigital capacitors is proposed. The utilized coupled lines structure reduced the configuration in size, as small as a few degrees. Moreover, the characteristic of interdigital capacitor, relatively high Q and good capacitance tolerance, accounts for the satisfied performance of this new filter. A two-stage bandpass filter was designed and fabricated with chip surface area only $1.02{\times}1.4\;mm^2$.

다층 유전체위의 다중 결합선로에 대한 유한차분법(FDTD)을 이용한 해석

  • 김윤석
    • 한국군사과학기술학회지
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    • 제3권1호
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    • pp.155-163
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    • 2000
  • A general characterization procedure based on the extraction of a 2n-port admittance matrix corresponding to n uniform coupled lines on the multi-layered substrate using the Finite-Difference Time-Domain (FDTD) technique is presented. The frequency-dependent normal mode parameters are obtained from the 2n-port admittance matrix, which in turn provides the frequency-dependent distributed inductance and capacitance matrices. To illustrate the technique, several practical coupled line structures on multi-layered substrate, including a three-line structure, have been simulated. It is shown that the FDTD based time domain characterization procedure is an excellent broadband simulation tool for the design of multiconductor coupled lines on multilayered PCBs as well as thick or thin hybrid structures.

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밀결합 전송선 상에서 전력 저감을 위한 코드워드 생성 기법 (A Codeword Generation Technique to Reduce Dynamic Power Consumption in Tightly Coupled Transmission Lines)

  • 임재호;김덕민;김석윤
    • 대한전자공학회논문지SD
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    • 제48권11호
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    • pp.9-17
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    • 2011
  • 반도체 공정의 발달로 인해 칩의 집적도가 높아졌으며, 연결선 사이의 간격 또한 좁아지게 되었다. 그로 인해 연결선 내에 존재하는 커패시턴스와 인덕턴스가 증가하게 되었고, 특히 전역 연결선들에서는 자신의 그라운드 커패시턴스보다 인접한 다른 연결선과의 결합 커패시턴스가 더욱 커지는 경향을 보이게 되었다. 이러한 현상으로 인해 발생하는 유도성 결합과 용량성 결합은 인접한 연결선의 신호 간섭으로 심각한 문제를 야기할 수 있다. 본 논문에서는 추가적인 연결선을 이용하여 신호 무결성을 저해시키는 누화잡음을 제거하면서, 입력 데이터의 확률을 고려하여 동적 전력 소모를 최소화하는 코드워드 생성 기법을 제안하였다. 제안한 기법의 성능평가를 위해 FastCap 및 FastHenry 프로그램과 HSPICE를 이용하여 실험한 결과, 소모 전력에서 기존 기법보다 평균 15% 정도의 감소를 보임을 확인하였다.

세 개의 마이크로스트립 전송선로간의 크로스톡 (Crosstalk among three microstrip transmission lines)

  • 최재연;이상설
    • 전자공학회논문지D
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    • 제34D권5호
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    • pp.14-21
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    • 1997
  • The crosstalk among three identical uniform coupled microstrip transmissiom lines is examined. To analyze the crosstalk, the simultaneous equations for the voltage and current waves on each transmission line are induced from the transmission line equation. The capacitance and the inductance of the line to solve the transmission line equation are calculated by the spectral domain analysis and the space domian analysis. There are three quasi-TEM modes is three microstrip transmission lines and the characteristics mode impedences in each mode are almost equal at a weak coupling state. The crosstalk among three identical microstrip transmission lines is calculated varying the frequency from 50MHz to 3GHz.

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Experimental Characterization-Based Signal Integrity Verification of Sub-Micron VLSI Interconnects

  • Eo, Yung-Seon;Park, Young-Jun;Kim, Yong-Ju;Jeong, Ju-Young;Kwon, Oh-Kyong
    • Journal of Electrical Engineering and information Science
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    • 제2권5호
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    • pp.17-26
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    • 1997
  • Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

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유한 요소 해석에 의한 평면형 결합 선로의 설계 파라미터 추출 (Extraction of Design Parameters for Planar Coupled Lines)

  • 이필용;박준석;안달;김헝석
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 C
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    • pp.2213-2215
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    • 2000
  • In this paper we implemented a novel re-entrant mode microstrip directional coupler for realizing the high directivity characteristic using finite element (FE) analysis. In microstrip configuration, the high directivity can be reached by matching the even- and odd-mode effective phase velocities. Through the values of capacitance obtained from 2-dimensional finite element(FE) analysis, the phase velocities for each mode and the design parameter were extracted for the proposed coupled-line configuration. Based on the extracted design parameter with phase matching condition we designed and fabricated 30dB directional coupler at 850MHz. Experimental results show good performance with excellent isolation.

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