• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.236-238
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• 2005

In this paper, we propose a new discrete-time predictive current controller for a PMLSM(permanent magnet linear synchronous motor). The main objectives of the current controllers are that the measured stator current is tracked the command current value accurately and the transient interval is shorten as much as possible, in order to obtain high-performance of ac drive system. The conventional predictive current controller is hard to implement in full digital current controller since a finite calculation time causes a delay between the current sensing time and the time that take to apply the voltage to motor. A new control strategy is the schema that gets the fast adaptation of transient current change, the fast transient response tracking. Moreover, the simulation results will be verified the improvements of Predictive controller and accuracy of the current controller.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.652-657
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• 1992

This paper presents to accomplish successfully a multi-input real time control by applying control hierarchy for sliding mode of multi-joint manipulators whose nonlinear terms are regarded as disturbances. We- could simplify the dynamic equations of a manipulator and servo system, which are composed of linear elements and nonlinear elements, by assuming that nonlinear terms, which are Inertia term, gravity force term, Coriolis force term and centrifugal force term, are external disturbance. By simplifying that equation, we could easily obtain a control input which satisfy sliding mode of multi-input system. We proposed a new control input algorithm in order to decrease chattering by changing control input according as effect of disturbance if a control response become within allowance error range. In this experiments, we used DSP(Digital Signal Processor) controller to suppress chattering by time delay of calculation and to carry out real time control.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1169-1172
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm consider area and delay time is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. The proposed algorithm is examined by using benchmarks in SIS. In the case of that the number of OR-terms is 5, the experiments results show that reduce the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively.

• The Journal of the Acoustical Society of Korea
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• v.38 no.6
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• pp.630-636
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• 2019

Passive Ranging Sonar (PRS) is a type of passive sonar consisting of three sub-array on the port and starboard, and has a characteristic of detecting a target and calculating a bearing and a distance. The bearing and distance calculation requires physical sub-array position information, and the bearing and distance accuracy performance are deteriorated when the position information of the sub-array is inaccurate. In particular, it has a greater impact on distance accuracy performance using plus value of two time-delay than a bearing using average value of two time-delay. In order to improve this, a study on sub-array position error estimation and error compensation is needed. In this paper, We estimate the sub-array position error based on enetic algorithm, an optimization search technique, and propose a method to improve the performance of distance accuracy by compensating the time delay error caused by the position error. In addition, we will verify the proposed algorithm and its performance using the sea-going data.

• Journal of the Korea Society of Computer and Information
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• v.20 no.7
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• pp.9-16
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• 2015

This paper proposes the parallel design of a shot change detection algorithm using frame segmentation and moving blocks. In the proposed approach, the high parallel processing components, such as frame histogram calculation, block histogram calculation, Otsu threshold setting function, frame moving operation, and block histogram comparison, are designed in parallel for NVIDIA GPU. In order to minimize memory access delay time and guarantee fast computation, the output of a GPU kernel becomes the input data of another kernel in a pipeline way using the shared memory of GPU. In addition, the optimal sizes of CUDA processing blocks and threads are estimated through the prior experiments. In the experimental test of the proposed shot change detection algorithm, the detection rate of the GPU based parallel algorithm is the same as that of the CPU based algorithm, but the average of processing time speeds up about 6~8 times.

• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.470-474
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• 2005

There are many suggestion of methods which get good quality images by controling the GOP structure. But the existing algorithm should have not good to deal the real time adaptive processing determine the GOP structure because which check the fixed quantity of image in advance and require high capacity of frame memories and have delay time by increasing calculation quantity. This paper propose the algorithm which adapt the real time by the basic of macro block. We show the good simulation results using the proposed GOP structure based on macro block.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2001.05a
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• pp.207-212
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• 2001

In this paper, a method to be able to decide the possible maximum gain of P, PI control for the retarded processes under stable condition is proposed. At first, adjustable parameter set causing stability limit are obtained based on the frequency domain condition which makes the roots of transfer function locate on the $j\omega$ axis. And the cut-in frequency $\omega{_p}$ to bring the parameter set to P control from PI control is derived by an equation with 2 parameters L and $T_m$ given, then $\omega{_p}$ is used to compute the maximum gain with stable condition. For the calculation, the controlled process of first order system with time delay element is introduced and all parameters are presumed to be time invariant.

• Korean Journal of Construction Engineering and Management
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• v.24 no.1
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• pp.12-20
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• 2023

To calculate the amount of owner-caused and contractor-caused delays based on a simplified delay analysis, which has been customarily used in Korea, has a limitation in reflecting the impact of the concurrent delay and the acceleration work. It also resulted in the apportionment of liquidated damages by applying the ratio of the number of delays between the owner and the contractor. This study analyzes that the conventional method does not meet the international standards. In order to improve the problem of construction delay analysis and the apportionment of liquidated damages based on it, owner delays, contractor delays, concurrent delays, and the impact of acceleration should be analyzed together. This study suggests that in the apportionment of liquidated damages, the extension of time should be extended by the sum of concurrent delays and the owner-caused delays, and liquidated damages should be imposed on delays incurred after the extension of time. It can be seen that it conforms to the international standards. The results of this study are expected to contribute to improving the problems of delay analysis and liquidated damages calculation, which have been conventionally accepted.

• Journal of IKEEE
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• v.18 no.4
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• pp.509-516
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• 2014

CRC feature in a high-speed semiconductor memory devices such as DDR4/GDDR5 increases the data reliability. Conventional CRC method have a massive area overhead and long delay time. It leads to insufficient internal timing margins for CRC calculation. This paper, presents a CRC code method that provides error detection and a real-time matrix type CRC. If there are errors in the data, proposed method can alert to the system in a real-time manner. Compare to the conventional method(XOR 6 stage ATM-8 HEC code), the proposing method can improve the error detection circuits up to 60% and XOR stage delay by 33%. Also the real-time error detection scheme can improve the error detection speed to agerage 50% for the entire data bits(UI0~UI9).

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.136-142
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• 2013

CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.