• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.385-385
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• 2012

A two terminal N+/P/N+ junction device to replace the conventional selective transistor was studied as a bilateral switching device for spin transfer torque (STT) MRAM based on 3D device simulation. An N+/P/N+ junction structure with $30{\times}30nm$ area requires bi-directional current flow enough to write a data by a drain induced barrier lowering (DIBL) under a reverse bias at N+/P (or P/N+ junction), and high current on/off ratio of 106. The SiGe materials are widely used in hetero-junction bipolar transistors, bipolar compensation metal-oxide semiconductors (BiCMOS) since the band gap of SiGe materials can be controlled by changing the fraction and the strain epilayers, and the drift mobility is increased with the increasing Ge content. In this work, N+/P/N+ SiGe material based junction provides that drive current is increased from 40 to $130{\mu}A$ by increased Ge content from 10~80%. When Ge content is about 20%, the drive current density of SiGe device substantially increased to 2~3 times better than Si-based junction device in case of 28 nm P length, which is sufficient current to operation of STT-MRAM.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1001-1006
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• 2005

A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.175-177
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• 2002

Electrical characteristics of the Si-O superlattice diode as a function of annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice diode with multilayer Si-O structure showed the stable and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator (SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.19-22
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• 2003

In this paper, Si anisotropic etching characteristics of tetramethylammonium hydroxide (TMAH)/ammonium persulfate (AP) solutions were investigated to realize the optimum structure of a diaphragm for the piezoresistive pressure sensor application. Due to its low toxicity and its high compatibility with the CMOS processing, TMAH was used as Si anisotropic etchants. The variations of Si etch rate on the etching temperature, TMAH concentration, and etching time were obtained. With increasing the etching temperature and decreasing TMAH concentrations, the Si etch rate is increased while a significant non-uniformity exists on the etched surface because of formation of hillocks on the <100> surface. With the addition of AP to TMAH solution, the Si etch rate is increased and an improvement in flatness on the etching front is observed. The Si etch rate is also maximized with increasing the number of addition of AP to TMAH solution per one hour. The Si square diaphragms of 20$\mu\textrm{m}$ thickness and 100-400 $\mu\textrm{m}$ one-side length were fabricated successfully by adding AP of (5/6)g to 800 ml TMAH solution every 10 minutes.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Proceedings of the IEEK Conference
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• summer
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• pp.82-85
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• 2004

This paper proposes an advanced circuit for the capacitive type fingerprint sensor signal processing and an effective isolation structure for minimizing an electrostatic discharge(ESD) influence and for removing a signal coupling noise of each sensor pixel. The proposed detection circuit increases the voltage difference between a ridge and valley about $80\%$ more than old circuit. The test chip is composed of $160\;\times\;192$ array sensing cells $(9,913\times11,666\;um^2).$ The sensor plate area is $58\;\times\;58\;um^2$ and the pitch is 60um. The image resolution is 423 dpi. The chip was fabricated on a 0.35um standard CMOS process. It successfully captured a high-quality fingerprint image and performed the registration and identification processing. The sensing and authentication time is 1 sec(.) with the average power consumption of 10 mW at 3.0V. The reveal ESD tolerance is obtained at the value of 4.5 kV.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.329-335
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• 2011

In this paper, a dual-band integer-N frequency divider is proposed for 2.4/5.2 GHz multi-standard wireless local area networks. It consists of a multi-modulus imbalance phase switching prescaler and two all-stage programmable counters. It is able to provide dual-band operation with high resolution while maintaining a low power consumption. This frequency divider is integrated with a 5 GHz VCO for multi-standard applications. Measurement results show that the VCO with frequency divider can work at 5.2 GHz with a total power consumption of 22 mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.