• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1197-1200
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• 2003

This paper presents A/D converter for the signal processing of infrared sensor and CMOS image sensor. The A/D converter designed in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW at 2.5V supply voltage. This A/D converter is based on a pipeline architecture in which the number of bits converted per stage and the stage number are optimized to achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.597-602
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• 2013

In this paper, the lens module of mega pixel type was designed for barrel distortion calibration due to the barrel distortion of ultra wide angle. And the performance of this camera module was improved with the images from wide dynamic range 2 megapixel CMOS image sensor.

• Journal of Sensor Science and Technology
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• v.18 no.4
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• pp.280-285
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• 2009

In this paper, we designed a 2-stage CMOS operational amplifier with temperature compensation function using 2-poly 4-metal 0.35 $\mu$m standard CMOS technology. Using two bias circuits, the positive temperature coefficient(PTC) and the negative temperature coefficient(NTC) of the bias circuit are canceled out each other. When reference current circuit is simulated that it has a temperature coefficient of -150 ppm/$^{\circ}C$ with a temperature change from 0 $^{\circ}C$ to 120 $^{\circ}C$. Also the proposed circuit has a temperature coefficient of -0.011 dB/$^{\circ}C$ of DC open loop gain with the same temperature range.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• ETRI Journal
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• v.29 no.1
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• pp.70-78
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• 2007

A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow low-voltage circuit operation. A simple 1-bit first-order delta-sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 ${\mu}m$ CMOS technology and draws less than 200 ${\mu}A$ from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non-linearity error.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• Journal of Sensor Science and Technology
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• v.20 no.6
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• pp.428-433
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• 2011

We report on the building of a micro sensor array based on typical semiconductor fabrication processes aimed at monitoring selectively a specific gas in ambient of other gases. Chemical sensors can be applied for an electronic nose and/or robots using this technique. Microsensor array was fabricated on the same chip using 0.6${\mu}m$ CMOS technology, and unique gas sensing patterns were obtained by principal component analysis from the array. $SnO_2$/Pt sensor for CO gas showed a high selectivity to buthane gas and humidity. $SnO_2$ sensor for hydrogen gas, however, showed a low selectivity to CO and buthane gas. We can obtain more distinguishable patterns that provide the small sensing deviation(the high seletivity) toward a given analyte in the response space than in the chemical space through the specific parameterization of raw data for chemical image formation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.6
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• pp.553-558
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• 2016

A DC-DC converter for CMOS image sensors in bio-sensor chips is proposed. The DC-DC converter generates a PCP voltage, that is an on voltage of a pixel, and an NCP voltage, that is an off voltage of a pixel. The PCP voltage with a ripple voltage of within 1.33V is obtained from a positive charge pump of VPP (=5V) with a ripple voltage of 45.35 by using a regulator. Also, the NCP voltage with a ripple voltage of 0.05mV is obtained from a negative charge pump of VNN (=-2V) with a ripple voltage of 62.8 by using a regulator.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.77-86
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• 1998

A two-chip humidity sensor system has been developed which consists of a capacitive sense element die and a CMOS interface chip. The sense element was fabricated using thin polyimide films on (100) silicon substrate and showed excellent linearity(0.72%FS), low hysteresis (<3%) and low temperature coefficient(-0.0285 ~-0.0542pF/K) over a wide range of relative humidity and temperature. The capacitance-relative humidity characteristic exhibited a drift of 2~3% after 9 weeks of exposure to 4$0^{\circ}C$/90%RH. The signal-conditioning circuitry was fabricated using an 1.2- ${\mu}{\textrm}{m}$, one poly double metal CMOS process. The measured output voltage of the sensor system was directly proportional to relative humidity and showed good agreement with theory.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.25-30
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• 2010

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.