• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.13-17
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• 2013

In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um ${\times}$ 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.89-94
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• 2007

For successful implementation of multi-standard transmitter, reconfigurable architecture and component design are essential. This paper presents a reconfigurable CMOS power amplifier designed CMOS 0.25 um process. Designed power amplifier can be operated at 0.9, 1.2, 1.75, and 1.85 GHz. Also, it can be used at 2.4 GHz by using bonding wire inductor. The interstage matching network is composed of two inductors and four switches, and operation frequency can be varied by controlling switches. Proposed power amplifier can be used as a power amplifier in low power applications such as ZigBee or Bluetooth application and used as a driver amplifier in high power application such as CDMA application. Designed power amplifier has 18.2 dB gain and 10.3 dBm output power at 0.9 GHz. Also, it represented 10.3 (18.1) dB gain and 5.2 (10) dBm output power at 1.75 (2.4) GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.25-31
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• 2017

This paper presents a 270/540/750/1500-Mb/s serial-data transmitter realized in a $0.13-{\mu}m$ CMOS technology for the applications of video data transmission. A low-cost RG-58 copper cable(5C-HFBT-RG6T) is exploited as a transmission medium connected to a single BNC connector, which shows cable loss 45 dB in maximum at 1.5 GHz. RLGC modeling provides an equivalent circuit for SPICE simulations of which characteristics are very similar to the measured cable loss. The loss can be compensated by pre-emphasis at transmitter and equalization at receiver if needed. Measurements of the proposed transmitter chip demonstrate the operations of 270-Mb/s, 540-Mb/s, 750-Mb/s and 1.5-Gb/s, and provide the output voltage levels of $370mV_{pp}$ at 1.5 Gb/s even with the pre-emphasis turned-off. The total power consumption is 104 mW from 1.2/3.3-V supplies and the chip occupies the area of $1.65{\times}0.9mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.52-57
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• 2011

This paper presents a 4-channel optical transmitter circuit realized in a $0.18{\mu}m$ CMOS technology for high-speed digital interface. Particularly, the VCSEL driver exploits the feed-forward technique, and the pre-amplifier employs the pulse-width control. Thus, the optical transmitter operates at the bias current up to 4mA and the modulation current from $2{\sim}8mA_{pp}$. with the pulse-width distortion compensated effectively. The 4-channel optical transmitter array chip occupies the area of $1.0{\times}1.7mm^2$ and dissipates 35mW per channel at maximum current operations from a single 1.8V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.402-403
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• 2011

This paper has proposed a $0.13-{\mu}m$ CMOS RF Front-end transmitter for LTE-Advanced systems. The proposed RF Front-end supports a band 7 (from 2500 MHz to 2570 MHz) in E-UTRA of 3GPP. It can provide a maximum output power level of +10 dBm but it's a normal output power level is +0 dBm considering a low PAPR. The post-layout simulation results show that the quadrature up-conversion mixer and a driver amplifier consumes 14 mA and 28 mA from a 1.2 V supply voltage respectively, while providing a output power level of 0 dBm at the input power level of -13 dBm.

• Journal of Power Electronics
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• v.12 no.6
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.16-25
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• 1997

This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.653-654
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• 2006

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.9
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• pp.27-36
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• 1992

A design of scanning electrode driving IC chip has been implemented aiming at the application to liquid crystal color television displays. The chip reflects the design characteristics of high quality liquid crystal panels and satisfies specifications of NTSC type color television displays. The design was verified using logic and circuit simulation, and fabricated using a high voltage CMOS process. A fully working die has been obtained that can be readily applicable to commercial color liquid crystal panels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.