• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.143-148
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• 2015

In this paper a new method is proposed for realizing active floating inductors from voltage differencing transconductance amplifier(VDTA) which is being studied nowadays. This proposed method employs only one VDTA and one transconductance for designing an active inductor from a passive floating inductor and implementing it to integrated circuits. The number of CMOS transistors can be considerably reduced from 6~18 as 1~3 gm circuits can be eliminated and even without R the design can be made, which can help in reducing the size of the circuit and power consumption. The proposed VDTA floating inductor was successfully used in constructing 1 MHz second order biquad active bandpass filter and bandwidth could be adjusted from 77kHz~1.59MHz by the changes made in gm from 6uS~20uS.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.77-84
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• 1998

A voltage controlled chaotic circuit has been designed in integrated circuit and fabricated by using 0.8$\mu\textrm{m}$ single poly CMOS technology. The fabricated chaotic circuit consist of sample and hold circuits, op-amps, nonlinear function generator and two phase clock generator. The test results of the chaotic circuit show that periodic state, quasi-periodic state and chaotic state can be obtained according to the input control voltage with the ${\pm}$2.5V power supply and clock rate of 20kHz. In addition, two dimensional chaotic patterns have been observed by connecting this circuit in parallel or series

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.231-238
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• 2013

This paper describes a DC-DC converter IC for Flat Panel Displays. In case of operate LCD devices various type of DC supply voltage is needed. This device can convert DC voltage from 6~14[V] single supply to -5[V], 15[V], 23[V], and 3.3[V] DC supplies. In order to meet current and voltage specification considered different type of DC-DC converter circuits. In this work a negative charge pump DC-DC converter(-5V), a positive charge pump DC-DC converter(15V), a switching Type Boost DC-DC converter(23V) and a buck DC-DC converter(3.3V). And a oscillator, a thermal shut down circuit, level shift circuits, a bandgap reference circuits are designed. This device has been designed in a 0.35[${\mu}m$] triple-well, double poly, double metal 30[V] CMOS process. The designed circuit is simulated and this one chip product could be applicable for flat panel displays.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• ETRI Journal
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• v.30 no.1
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• pp.33-46
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• 2008

This paper presents the experimental results of a low-power low-cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 ${\mu}m$ CMOS process and occupies 10 $mm^2$ of silicon area.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.309-314
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• 2014

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.217-218
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• 2008

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. A general method for achieving both reduced VCO gain(Kvco) and wide frequency band is to use the switched-capacitor bank LC VCO. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO with reduced variation of VCO gain and frequency steps. Buffers, divide-by-2 circuits and control logics the simulation results show that the designed circuit has a phase noise at 100kHz better than -106dBc/Hz throughout the signal band and consumes $9.5{\sim}13mA$ from a 1.8V supply.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1254-1257
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• 2004

This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.