• Journal of IKEEE
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• v.14 no.3
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• pp.232-235
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• 2010

A 60GHz active phase shifter with 65nm CMOS is presented by replacing passive switches in switched-line type phase shifter with active ones. Active-switch phase shifter is composed of active-switch blocks and passive delay network blocks. The active-switch phase shifter design is compact compare with the conventional vector-sum phase shifter. Active-switch blocks are designed to accomplish required input and output impedances whose requirements are different whether the switch is on or off. And passive delay network blocks are composed of lumped L,C instead of normal microstrip line to reduce the size of the circuit. An 1-bit phase shifter is fabricated by TSMC 65nm CMOS technology and measurement results present -4dB average insertion loss and 120 degree phase shift at 65GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.61-70
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• 2009

A 10b 30MS/s pipelined ADC operating under 1V power supply is presented. It utilizes a switched-RC based input sampling circuit and a resistive loop to reset the feedback capacitor in the multiplying digital-to-analog converter (MDAC) for the low-voltage operation. Cascaded switched-RC branches are used to achieve accurate grain of the MDAC for the first stage and separate switched-RC circuits are used in the sub-ADC to suppress the switching noise coupling to the MDAC input The measured differential and integral non-linearities of the prototype ADC fabricated in a 0.13${\mu}m$, CMOS process are less than 0.54LSB and 1.75LSB, respectively. The prototype ADC achieves 54.1dB SNDR and 70.4dB SFDR with 1V supply and 30MHz sampling frequency while consuming 17mW power.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.354-356
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• 2013

본 논문에서는 CMOS 스위치를 이용한 디지털 이득 제어 구조를 가진 이득 조절 증폭기 (PGA, Programmable Gain Amplifier)를 제안한다. 기존의 아날로그 이득 제어 방식에서는 가변적인 트랜스 컨덕턴스를 활용하는 과정에서 바이어스 전류나 전압에 의해 이득이 변하게 되어 순간적으로 구성회로의 바이어스 포인트가 변하기 때문에 왜곡이 발생하게 되는 문제점이 있다. 본 논문에서는 이러한 문제점을 해결하기 위해 기존의 gm-boosting 증폭기를 변형한 디지털 이득 제어 방식으로 설계되어 있기 때문에 우수한 선형성을 가지며 특수 목적에 맞도록 그 이득을 6dB에서 60dB까지 7가지 단계로 조절 가능하다. 제안한 PGA는 기존 회로에 비해 0.2dB 보다 작은 이득오차와 0.47mW의 낮은 소비전력 특성을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1245-1251
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• 1999

A 1.25Gb/s path control switch chip has been designed and implemented with COMPASS tool and 0.8${\mu}{\textrm}{m}$ CMOS gate-array of LG semiconductor. This device controls the path of digital singnals in SDH-based transmission system. The proposed switch chip is suitable for self-healing operations both in a linear network and an unidirectonal ring, The self-healing operation of the switch is effectively done by the configuration information stored in the resisters of the switch. The test device adapted to SDH-based transmission system, show immediate restoration and a 10-11~10-12 bit error raito. And 2.5Gb/s or more high throughput can be realized by combining rwo identical or more switches with the parallel architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.329-337
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• 1989

This paper describes a composition of time switch with a large capacity(NK byte) by multi-write method. The method arranged a basic unit in a plane and a group, which is composed by 1K byte time switch using a memory elements with a fixed access time and capacity. And the time switch of large capacity is composed by multi-write method, which is more than 8K byte capacity with many constraints by using today's semiconductor development techniques, then a basic unit is the 1K byte time switch using a CMOS SRAM with 62.5ns access time and 1K byte capacity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.12
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• pp.691-698
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• 2014

An L-band single side band(SSB) mixer with CMOS switches and a C-band quadrature voltage-controlled oscillator(QVCO) have been developed using the TowerJazz 0.18-um RFCMOS process. The SSB mixer exhibits a conversion gain of 6.6 ~ 7.5 dB with a 70-dBc image rejection ratio and 65-dBc port isolation. The oscillation frequency range of the QVCO is 6.2 ~ 6.7 GHz with an output power of 4~6 dBm. For measurement, 1.8 V supply voltage is used while drawing 36 mA for the mixer and 23 mA for the QVCO.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.201-210
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• 2002

This paper describes a 3.3 (V) low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS($\upsilon$MOS) down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6(MHz) and a power dissipation of 24.5 (mW) with a single power supply of 3.3 (V) for a CMOS 0.35${\mu}{\textrm}{m}$ n-well technology.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1111-1116
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• 2011

In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.