• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.12
• /
• pp.198-208
• /
• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.4
• /
• pp.136-141
• /
• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.1
• /
• pp.1-11
• /
• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

• The KIPS Transactions:PartA
• /
• v.18A no.6
• /
• pp.249-254
• /
• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.3 no.4
• /
• pp.787-794
• /
• 1999

This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• The Journal of the Acoustical Society of Korea
• /
• v.17 no.8
• /
• pp.12-18
• /
• 1998

본 논문에서는 개선된 elliptic 저역통과 함수를 제시하고, CMOS DDA 소자 및 DDA 응용회로를 이용하여 CDMA 무선 휴대폰용 아날로그 DDA 저역통과 필터를 설계하 였다. 개선된 elliptic 저역통과 필터 함수는 통과대역과 저지대역에서 점진적 감소 파상 특 성을 갖고, 우수 또는 기수 차수 모두에 대해서 ω=0에서는 통과대역의 최대값, ω=∞에서 는 영이 된다. 또한 극점-Q 값이 감소함에 따라 주파수 및 시간영역의 특성 등이 기존의 함수와 비교하여 향상되었다. 아날로그 능동 저역통과 필터는 수동 복종단 제자형 회로망의 저감도 특성이 유지되는 개구리 도약법으로 모의하고, 적분기등을 외부 소자와의 정합이 필 요 없는 DDA를 이용하여 설계하였다. 설계된 DDA 회로의 단위 이득 주파수는 1.32GHz이 고 이를 이용하여 DDA 저역통과 필터를 설계하여 HSPICE로 시뮬레이션한 결과 필터의 차단 주파수는 630KHz로 설계명세조건과 일치하였다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2004.10a
• /
• pp.556-558
• /
• 2004

최근 VLSI 설계 분야에서, 단열 논리는 에너지 효율성이 뛰어난 저전력 설계 기술 중 하나로 각광 받고 있다. 이러한 단열 논리는 기존의 저전력 회로 설계를 위해 사용되었던 CMOS 논리들을 서서히 대체해 나갈 컷으로 기대되고 있다. 하지만 않은 단열 논리들의 제시에도 불구하고, 기존의 CMOS논리들을 단열 논리로 대체하는 기법에 관한 연구는 거의 없는 실정이다. 이 논문에서는 래치형 패스 트랜지스터 단열 논리(LPAL)와 이를 이용한 저전력 설계 기법을 소개하였다. 래치형 패스 트랜지스터 단열 논리는 기존의 단열 논리들이 가지고 있는 단정을 해결하고, 보다 저전력 지향적으로 CMOS논리를 대체 할 수 있다는 장점을 가진다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.3 s.357
• /
• pp.6-11
• /
• 2007

This paper proposes CMOS optical receivers to reduce effective area and pulse width distortion (PWD) in high definition digital audio interfaces. To mitigate effective area and PWD, proposed receivers include a frans-impedance amplifier (TIA) with dual output and a level shifter with threshold convergence, respectively. Proposed circuits are fabricated using $0.25{\mu}m$ CMOS process and measured result demonstrated the effective area of $270\times120{\mu}m^2$ and PWD of ${\pm}3%$ for the receiver with a dual output TIA, and the effective area of $410\times140{\mu}m^2$ and PWD of ${\pm}2%$ for the receiver with a threshold convergence level shifter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.398-401
• /
• 2011

This paper presents a high-efficiency CMOS PWM DC-DC buck converter. It generates a constant output voltage(1-2.8V), from an input voltage(3.4-3.9V). Inductor-based type is chosen and inductor current is controlled with PWM operation. The designed circuit consists of power switch, Pulse Width Generation, Buffer, Zero Current Sensing, Current Sensing Circuit, Clock & Ramp generation, V-I Converter, Soft Start, Compensator and Modulator. Switching Frequency is 1MHz, It operates in CCM when the load current is more than 40mA, and the maximum efficiency is 98.71% at 100mA. Output voltage ripple is 0.98mV(input voltage:3.5V, output voltage:2.5V). The performance of the designed circuit has been verified through extensive simulation using a CMOS $0.18{\mu}m$ technology.

• The KIPS Transactions:PartA
• /
• v.14A no.4
• /
• pp.203-208
• /
• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.