• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.33-39
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• 2014

In this paper, a new on-chip aging sensing circuit based on flip-flops is proposed to detect a circuit failure of MOSFET digital circuits casued by aging phenomenon such as HCI and BTI. The proposed circuit uses timing windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur. The generated bits can apply to an adaptive self-tuning method for reliable system design as control signals. The aging sensor circuit has been implemented using 0.11um CMOS technology and evaluated by $4{\times}4$ multiplier with power gating structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2933-2938
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• 2014

In this paper, the FLL(Frequency Locked Loop) circuit using current conveyor circuit is designed by $0.35{\mu}m$ CMOS process. The FLL circuit is built in a frequency divider, a frequency-to-voltage converter, a voltage subtractor and a oscillator and the circuit blocks have a symmetric structure to improve a reliability characteristics with a process variation. From the simulation results, the variation rate of output frequency is about less than ${\pm}1%$ when the channel length, channel width, resistance and capacitance are varied ${\pm}5%$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.7
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• pp.885-890
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• 2020

In the distance measurement system the time-to-digital conversion circuit used measures the distance using the time interval between the start signal and the stop signal. The time interval is generally converted to digital information using a counter circuit considering the response speed. Therefore, a clock signal with a high frequency is required to improve precision, and a clock signal with a high frequency is also required to measure fine distances. In this paper, a counter circuit was designed to increase the accuracy of distance measurement while using the same frequency. The circuit design was performed using a 0.18㎛ CMOS process technology, and the operation of the designed circuit was confirmed through HSPICE simulation. As a result of the simulation, it is possible to obtain an improvement of four times the precision compared to the case of using a general counter circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.67-74
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• 2014

This paper presents a memristor-CMOS based RBSD adder. Conventional RBSD adders suffer bigger hardware due to the extra logic handling larger number of bits. The purpose of this paper is to improve the silicon surface area and the computation delay of conventional RBSD adders. The proposed method employs memristor-CMOS based circuit. The implementation results shows that the proposed memristor-CMOS based RBSD adder saves the cell area by 45%, and reduces time delay 24% compared to conventional RBSD adders. The proposed RBSD adder design can bring further area saving for large scale designs.

• The Magazine of the IEIE
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• v.19 no.6
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• pp.55-60
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• 1992

본 논문은 ISDN U-interface 회로 중에서 digital 부분의 설계에 대하여 기술하였다. 이 회로는 MMS43 code와 echo cancellation 방식을 사용하여 구현되었다. 회로 구성상 interface부분과 DSP부분으로 나누어 설계하였으며 gate-array ASIC을 이용하여 chip을 제작하였다. 공정은 1um CMOS 기술을 사용하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.1-9
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• 2008

This paper suggests the triple-mode CMOS DC-DC converter that has temperature/voltage variation compensation techniques. The proposed triple-mode CMOS DC-DC converter is used to generate constant or variable voltages of 0.6-2.2V within battery source range of 3.3-5.5V. Also, it supports triple modes, which include Pulse Width Modulator (PWM) mode, Pulse Frequency Modulator (PFM) mode and Low Drop-Out (LDO) mode. Moreover, it uses 1MHz low-power CMOS ring oscillator that will compensate malfunction of chip in temperature/voltage variation condition. The proposed triple-mode CMOS DC-DC converter, which generates output voltages of 0.6-2.2V with an input voltage sources of 3.3-5.5V, exhibits the maximum output ripple voltage of below 10mV at PWM mode, 15mV at PFM mode and 4mV at LDO mode. And the proposed converter has maximum efficiency of 93% at PWM mode. Even at $-25{\sim}80^{\circ}C$ temperature variations, it has kept the output voltage level within 0.8% at PWM/PFM/LDO modes. For the verification of proposed triple-mode CMOS DC-DC converter, the simulations are carried out with $0.35{\mu}m$ CMOS technology and chip test is carried out.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.9
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• pp.1-7
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• 1992

This paper proposes a built-in self-test tchnique for CMOS circuits. To detect a stuck-open fault in CMOS circuits, two consequent test patterns is required. The ordered pairs of test patterns for stuck-open faults are generated by feedback shift registers of extended length. A nonlinear feedback shift register is designed by the merging method and reordering algorithms of test patterns proposed in this paper. And a new multifunctional BILBO (Built-In Logic Block Observer) is designed to perform both test pattern generation and signature analysis efficiently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.89-93
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• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.877-882
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• 2016

In this paper, a novel CMOS high Q factor 2-port active inductor has been proposed. The proposed circuit is designed by cascading basic gyrator-C structural active inductors and attaching the feedback LC resonance circuit. This LC resonator can compensate parasitic capacitance of transistor and can improve Q factor over wide frequency range. The proposed circuit was fabricated and simulated using 65 nm Samsung RF CMOS process. The fabricated circuit shows inductance of above 2 nH and Q factor higher than 40 in the frequency range of 1~6 GHz.