• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.736-748
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• 2003

Dynamic voltage scaling(DVS), which adjusts the clock speed and supply voltage dynamically, is an effective technique in reducing the energy consumption of embedded real-time systems. The energy efficiency of a DVS algorithm largely depends on the performance of the slack estimation method used in it. In this paper, we propose novel DVS algorithms for periodic hard real-time tasks based on an improved slack estimation algorithm. Unlike the existing techniques, the proposed method can be applied to most priority-driven scheduling policies. Especially, we apply the proposed slack estimation method to EDF and RM scheduling policies. The experimental results show that the DVS algorithms using the proposed slack estimation method reduce the energy consumption by 20∼40 % over the existing DVS algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.285-289
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• 2003

This paper proposes a 10 ${\mu}{\textrm}{m}$ thick oxide air-bridge structure which can be used as a substrate for RF circuits. The structure was fabricated by anodic reaction, complex oxidation and rnicrornachining technology using TMAH etching. High quality films were obtained by combining low temperature thermal oxidation (50$0^{\circ}C$, 1 hr at $H_2O$/O$_2$) and rapid thermal oxidation (RTO) process (105$0^{\circ}C$, 2 min). This structure is mechanically stable because of thick oxide layer up to 10 ${\mu}{\textrm}{m}$ and is expected to solve the problem of high dielectric loss of silicon substrate in RF region. The properties of the transmission line formed on the oxidized porous silicon (OPS) air-bridge were investigated and compared with those of the transmission line formed on the OPS layers. The insertion loss of coplanar waveguide (CPW) on OPS air-bridge was (about 1 dB) lower than that of CPW on OPS layers. Also, the return loss of CPW on OPS air-bridge was less than about - 20 dB at measured frequency region for 2.2 mm. Therefore, this technology is very promising for extending the use of CMOS circuitry to higher RF frequencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.23-29
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• 2012

The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• Journal of IKEEE
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• v.17 no.1
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• pp.77-82
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• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

• Journal of the Korean Vacuum Society
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• v.19 no.2
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• pp.141-147
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• 2010

In this study, high-k oxide films like $Al_2O_3$, $TiO_2$, $HfO_2$ were deposited on Si, $SiO_2$/Si, GaAs wafers, and then the thermal conductivity was measured by using thermo-reflectance method which utilizes the reflectance variation of the film surface produced by the periodic temperature variation. The result shows that high-k oxide films with 50 nm thickness have high thermal conductivity of 0.80~1.29 W/(mK). Therefore, effectively dissipate the heat generated in the electric circuit such as CMOS memory device, and the heat transfer changes according to the micro grain size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.9
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• pp.1158-1165
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• 2021

This paper proposes a CNN accelerator which is optimized Pooling layer operation incorporated in Multiplication And Accumulation(MAC) to reduce the memory size. For optimizing memory and data path circuit, the quantized 8bit integer weights are used instead of 32bit floating-point weights for pre-training of MNIST data set. To reduce chip area, the proposed CNN model is reduced by a convolutional layer, a 4*4 Max Pooling, and two fully connected layers. And all the operations use specific MAC with approximation adders and multipliers. 94% of internal memory size reduction is achieved by simultaneously performing the convolution and the pooling operation in the proposed architecture. The proposed accelerator chip is designed by using TSMC65nmGP CMOS process. That has about half size of our previous paper, 0.8*0.9 = 0.72mm². The presented CNN accelerator chip achieves 94% accuracy and 77us inference time per an MNIST image.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.10
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• pp.895-903
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• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.