• ETRI Journal
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• v.22 no.1
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• pp.20-29
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• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.9
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• pp.720-727
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• 2008

Microfluidic single chip integrating thermopneumatic micropump and micro check valve are developed. The micropump and micorvalve are made of biocompatible materials, glass and PDMS, so as to be applicable to the biochip. By using the passive-type check valve, backward flow and fluid leakage are blocked and flow control is stable and precise. The chip is composed of three PDMS layers and a glass substrate. In the chip, flow channel and pump chamber were made on the PDMS layers by the replica molding technique and pump heater was made on the glass substrate by Cr/Au deposition. Diameter of the pump chamber is 7 mm and the width and depth of the channel are 200 and $180{\mu}m$, respectively. The PDMS layers chip and the heater deposited glass chip are combined by a jig and a clamp for pumping operation, and they are separable so that PDMS chip is used as a disposable but the heater chip is able to be used repeatedly. Pumping performance was simulated by CFD software and investigated experimentally. The performance was the best when the duty ratio of the applied voltage to the heater was 33%.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.1
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• pp.64-69
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• 2005

In this paper, we analyzed the nonlinear performance on the DS/CDMA Communication System. At the $BER=10^{-4}$, uniform chip waveforms have similar performance in the linear channel. However, non-uniform chip waveforms have about more 0.5[dB] power gain than the conventional raised-cosine chip waveforms. In the nonlinear HPA, non-uniform chip waveforms have worse BER performance than the uniform chip waveforms because of the high PAPR. In other words, non-uniform chip waveforms show similar performance as uniform chip waveforms if IBO (input back on) of 15[dB] is given.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

• Journal of the Korean Society for Heat Treatment
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• v.25 no.1
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• pp.14-21
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• 2012

The effects of cutting condition and tempering temperature for the shape of cutting chip were investigated. For this purpose, a lead-free brass containing 1wt.% of Bi extruded at $750^{\circ}C$ in straight turning was used in this study. The cutting chip preferred was mainly found to be loose form of arc chips with curling discontinuity, and these were formed by shear fracture. However, some of fragmental element chip were found to be mixed when tempering temperature was as high as $500^{\circ}C$. The form and size of chip was more affected by feed rate than by tempering temperature and cutting rate. In addition, the cutting surface was observed to be formed more rough in the case of high feed rate and low cutting rate compared to low feed rate and high cutting rate.

• KSBB Journal
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• v.28 no.4
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• pp.254-259
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• 2013

Herein we present a diagnostic paper chip that can quantitatively detect albumin without external electronic reader and dispensing apparatus. We fabricated a diagnostic paper chip device by printing wax barrier on the paper and wicking it with citrate buffer and tetrabromophenol blue to detect albumin in sample solution. The paper chip is so simple that we dropped a sample solution at sample pad and measure the ratio of two travel distances of the sample solvent and albumin under the name of retention factor. Our result confirmed that the retention factor was constant in the samples with same concentration of albumin and useful determinant for the measurement of albumin concentration. The paper chip is affordable and equipment-free, and close to ideal point-of-care test in accordance with the assured criteria, outlined by the World Health Organization. We assume that this diagnostic paper chip will expand the concept of colorimetric determination and provide a inexpensive diagnostic method to aging society and developing country.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.470-480
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• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.65-70
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• 2015

In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.10
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• pp.676-681
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• 2015

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.