• ETRI Journal
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• 제30권2호
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• 대한임베디드공학회논문지
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• 제12권4호
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• 대한전자공학회논문지SD
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• 제46권2호
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• pp.57-63
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• 2009

본 논문에서는 빠른 Acquisition time을 갖는 새로운 구조의 수동형 광 통신망에서 쓰이는 버스트 모드 수신기용 622Mbps급 클럭/데이터 복원회로를 제안하고, 이를 구현하였다. 제안된 회로는 CDR(Clock and Data Recovery) 블록과 PLL(Phase Locked Loop) 블록으로 나뉘며, CDR 블록은 클럭이 입력 데이터에 연동되어 지터가 내제된 입력 데이터에도 항상 최적의 샘플링 시점을 갖도록 설계하였다. PLL블록은 Multi-phase generation VCO를 통해 위상이 서로 다른 8개의 클럭을 CDR블록에 제공한다. 제안된 회로는 $0.35{\mu}m$ CMOS 공정을 이용하여 설계 및 레이아웃을 하였고, 시뮬레이션을 위해 $2^7-1$ PRBS 입력데이터를 사용하였다. 시뮬레이션 결과 Peak-to-Peak 지터는 17ps의 복원된 데이터 지터 특성을 가지며, 입력된 데이터는 손실 없이 복원하는 것을 확인하였다.

• ETRI Journal
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• 제34권1호
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• pp.35-43
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• 2012

This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-${\mu}m$ CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.193-199
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• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• 전자공학회논문지SC
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• 제46권1호
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• pp.68-75
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• 2009

본 논문에서는 이중 보간 방식을 기반으로 1/4-rate 클록을 이용하는 효율적인 CDR을 제안하였다. 제안한 CDR은 다채널 송수신기에서 다중 위상 클록을 이용하여 클록 주파수를 줄일 경우 필요한 클록의 수가 증가하여 이들 클록을 공급할 때 소모되는 전력과 하드웨어적 부담이 증가한다는 단점을 극복하는 것을 목표로 설계되었다. 이를 위해 1/2-rate 클록 방식과 동일한 공급 클록 수를 유지하면서 각각의 복원부에서 추가로 필요한 클록을 플립플롭을 이용하지 않고 인버터만으로 생성하였다. 이로 인해 보다 높은 전송률의 요구 시 장애 요인 중 하나인 클록 생성기의 주파수를 낮추어 고속 전송을 가능케 하였으며, 공급 클록의 수를 증가시키지 않고 1/4-rate 주파수의 클록을 이용함으로써 CDR을 저전력화하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.287-292
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• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• 전기학회논문지
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• 제60권2호
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• 전기학회논문지
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• 제61권2호
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• pp.324-328
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• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.