• ETRI Journal
• /
• v.30 no.2
• /
• pp.275-281
• /
• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.12 no.4
• /
• pp.239-246
• /
• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.57-63
• /
• 2009

In this Paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuit is composed of CDR(Clock and Data Recovery) block and PLL(Phase Locked Loop) block. Lock dynamics is accomplished on the first data transition and data are sampled in the optimal point. The CDR circuit is realized in 0.35um CMOS process technology. With input pseudo-random bit sequences(PRBS) of $2^7-1$, the simulations show 17ps peak-to-peak retimed data jitter characteristics. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• ETRI Journal
• /
• v.34 no.1
• /
• pp.35-43
• /
• 2012

This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-${\mu}m$ CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.3
• /
• pp.193-199
• /
• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.188-193
• /
• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.1
• /
• pp.68-75
• /
• 2009

In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.287-292
• /
• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.2
• /
• pp.455-458
• /
• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.2
• /
• pp.324-328
• /
• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.