• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.755-764
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• 2004

Recently 'Banking IC Card Standard' and EMV Standard by the domestic standard is selected, and it is situation that is developing infrastructure vigorously to alternate Magnetic Stripe card by IC card. This paper analyzes EMV standard that is selecting public key cipher, and research wishes to study unexhausted EMV PKI relatively than internet PKI, WAP PKI etc. This paper propose utilizable EMV base Payment PKI model in IC card base payment system development, and developed EMV CA system with this. Also, this paper supplemented IC card Authentication mechanism that is defined in EMV standard, and propose 'Efficient smart card Authentication mechanism' to improve performance of this mechanism, and estimate performance.

• IT SoC Magazine
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• s.5
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• pp.54-57
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• 2005

• IT SoC Magazine
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• s.7
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• pp.52-53
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• 2005

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.527-530
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• 2004

High-temperature Superconductor(HTS) tubes were fabricated in term of different diameter, length and thickness by centrigugal forming method. For powder melting by induction the optimum range of melting temperatures and preheating temperature were $1050^{\circ}C{\sim}1100^{\circ}C\;amd\;550^{\circ}C$ for 30min, respectively. The mould renting speed was 1000rpm. A tube was annealed at $840^{\circ}C$ for 72hours in oxygen atmosphere. The plate-like grains were well developed along the renting direction and typical grain size was about more than $40{\mu}m$. It was found that Ic values increased with increasing the tube diameter while the Ic decreased with increasing tube thickness. Also Ic decreased with increasing the tube length. The measured Ic in $50mm{\times}70mm{\times}25mm$ tube was about 896Amp.

• Transactions of the Korean Society of Mechanical Engineers
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• v.14 no.4
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• pp.866-872
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• 1990

본 연구에서는 전보의 $J_{IC}$ 시험법 기교에 이어, 전기저항 가열로(splic furnace)와 고온용 신장계(high temperatuer extensometer)를 이용하여, 고온에서의 $J_{IC}$ 측정의 가능성을 검토하였으며, 고온용 신장계를 사용할 때와 COD게이지를 사용할 때의 $J_{IC}$값의 차이를 비교 검토하였다. 또한, 20.deg. C~600.deg. C에서, 온도 변화가 $J_{IC}$값에 미치는 영향에 대하여 고찰하여 보았다.

• Korean Chemical Engineering Research
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• v.43 no.5
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• pp.632-636
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• 2005

In this work, the effect of chemical treatments on surface properties of SiC was investigated in thermal and mechanical interfacial behaviors of SiC/PMMA nanocomposites. The acid/base value, contact angles, and FT-IR analysis were performed for the study of surface characteristics of the SiC studied. The thermal stabilities of the SiC/PMMA nanocomposites were investigated by thermogravimetric analysis (TGA). Also the mechanical interfacial properties of the composites were studied in critical stress intensity factor ($K_{IC}$) and critical strain energy release rate ($G_{IC}$) measurements. As a result, the acidically treated SiC (A-SiC) had higher acid value than that of untreated SiC (V-SiC) or basically treated SiC (B-SiC). The acidic solution treatment led to an increase in surface free energy of the SiC, mainly due to the increase of its specific component. Thermal and mechanical interfacial properties of the SiC/PMMA nanocomposites, including initial decomposition temperature (IDT), $K_{IC}$, and $G_{IC}$ had been improved in the acidic treatment on SiC. This was due to the improvement in the interfacial bonding strength, resulting from the acid-base interfacial interactions between the fillers and polymeric matrix.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.51-59
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• 1998

The purposes of the paper are to consider the failure phenomenon based on delamination and crack when the encapsulant of plastic IC package under hygrothermal loading in the IR soldering process is on elastic and viscoelastic behavior due to the temperature and to show the optimum design using fracture mechanics. The model for analysis is the plastic SOJ package with a dimpled diepad. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance to fracture by calculating J-integrals in low temperature and C(t)-integrals in high temperature with the change of the design under hygrothermal loading. The optimum design to depress the delamination and crack in the plastic IC package is presented.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.43-50
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• 1998

The purpose of the paper is to protect the damage of plastic IC package with searching the cause of the fracture due to the delamination and crack when the encapsulant of plastic IC package is on viscoelastic behavior with the effect of creep on high temperature, The model for analysis is the plastic SOJ package with dimpled diepad in the IR soldering process of surface mounting technology. The risk of delamination with calculating the distribution of viscoelastic thermal stress in the package without the crack in the surface mounting process is checked. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance against fracture in thermal loading with calculating C (t)-integrals according to the change of the design. The optimum design to depress the delamination and crack is presented.

• Advances in concrete construction
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• v.5 no.5
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• pp.513-537
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• 2017

In this study, the fracture toughness $K_{IC}$ of high performance concrete (HPC) was investigated by conducting three-point bending tests on a total of 240 notched beams of $500mm{\times}100mm{\times}100mm$ subjected to heating temperatures up to $450^{\circ}C$ with exposure times up to 16 hours and various heating and cooling rates. For a heating rate of $3^{\circ}C/min$, $K_{IC}$ for the hot concrete sustained a monotonic decrease trend with the increasing heating temperature and exposure time, from $1.389MN/m^{1.5}$ at room temperature to $0.942MN/m^{1.5}$ at $450^{\circ}C$ for 4-hour exposure time, $0.906MN/m^{1.5}$ for 8-hour exposure time and $0.866MN/m^{1.5}$ for 16-hour exposure time. For the cold concrete, $K_{IC}$ sustained a two-stage decrease trend, dropping slowly with the heating temperature up to $150^{\circ}C$ and then rapidly down to $0.869MN/m^{1.5}$ at $450^{\circ}C$ for 4-hour exposure time, $0.812MN/m^{1.5}$ for 8-hour exposure time and $0.771MN/m^{1.5}$ for 16-hour exposure time. In general, the $K_{IC}$ values for the hot concrete up to $200^{\circ}C$ were larger than those for the cold concrete, and an inverse trend was observed thereafter. The increase in heating rate slightly decreased $K_{IC}$, and at $450^{\circ}C$ $K_{IC}$ decreased from $0.893MN/m^{1.5}$ for $1^{\circ}C/min$ to $0.839MN/m^{1.5}$ for $10^{\circ}C/min$ for the hot concrete and from $0.792MN/m^{1.5}$ for $1^{\circ}C/min$ to $0.743MN/m^{1.5}$ for $10^{\circ}C/min$ for the cold concrete after an exposure time of 16 hours. The increase in cooling rate also slightly decreased $K_{IC}$, and at $450^{\circ}C$ $K_{IC}$ decreased from $0.771MN/m^{1.5}$ for slow cooling to $0.739MN/m^{1.5}$ for fast cooling after an exposure time of 16 hours. The fracture energy-based fracture toughness $K_{IC}$' was also assessed, and similar decrease trends with the heating temperature and exposure time existed for both hot and cold concretes. The relationships of two fracture toughness parameters with the weight loss and the modulus of rapture were also evaluated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.28-37
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• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.