• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.909-912
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• 1998

In this paper, a new connection admission controller using neural network is presented. The controller measures traffic flow, cell loss rate, and cell delay periodically. Using those measured information, it learns the distributions of traffics of each traffic. Also the proposed controller is able to measure and manage the delays that source traffics experience through the network by using DWRR multiplexer with buffers dedicated to each traffic source. Experimental result show that the heterogeneous traffic sources with various QoS requirement.

• East Asian mathematical journal
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• v.24 no.4
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• pp.407-414
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• 2008

Finite difference schemes are considered for a $Ca^{2+}$ diffusion equations with damping and convection terms, which describe $Ca^{2+}$ buffering by using stationary and mobile buffers. Stability and $L^{\infty}$ error estimates of approximate solutions for the corresponding schemes are obtained using the extended Lax-Richtmyer equivalence theorem.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.84.1-84
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• 2001

Funded by the Singapore National Science and Technology Board (NSTB), CAMTech is collaborating with a Singaporean research institute and two industry partners with the objective to improve electronics assembly processes. The goal of this project is to visualise the behaviour of an electronics assembly industry by simulating, visualising the discrete events of the entire manufacturing processes and observing the flow of materials, size of buffers, and line balancing. The traditional scenario - from the customer placing order for a product to delivery - goes through various phases including manufacturing the product. Several major electronics manufacturing stages can be addressed: fabrication, assembly ...

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.365-368
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• 1999

In this paper, we investigate the effect of adopting branch-penalty compensation schemes on the power performance of TLBs(Translation Look-aside Buffers) and instruction caches. We found that the double-buffer branch-penalty compensation scheme can reduce the power consumption of the TLBs and the instruction caches considered by up to 14-21.3%. The power consumption is estimated through simulation at the architectural level, using the Kamble/Ghose method

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.859-862
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• 1999

We designed a 128-tap FIR filter for a modem which complies with ITU-T V.32. We adopted pipeline technique and realized delay-taps with two ring-buffers. The multiplier in this filter carries out 2's complement fixed-point multiplication of 14bit $\times$ 16bit. The designed filter is expected to operate at 50MHz.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.160-164
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• 2000

Digital to analog converters based on the Josephson effect are promising for voltage standard, because they produce voltage steps with high precision and good stability. In this paper, we made a simulation study on RSFQ D/A converter. RSFQ D/A converter was composed of NDRO cells, T(toggle) flip-flops, D flip-flops, Splitters and Confluence Buffers. Confluence Buffer was used to reset the D/A converter. We also obtained operating margins of the important circuit values by simulational experiments.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.519-522
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• 1990

This paper formulates a problem of analysis and design of serial production lines, closed with respect to the number of carriers available in the system for parts transportation between operations. For two machines - two buffers systems, the paper gives an asymptotic solution and shows that optimization of the system with respect to the number of carriers available and the capacity of the feedback buffer may lead to substantial improvements of system's performance.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• Journal of applied mathematics & informatics
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• v.27 no.5_6
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• pp.1247-1256
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• 2009

Finite difference schemes are considered for a nonlinear $Ca^{2+}$ diffusion equations with stationary and mobile buffers. The scheme inherits mass conservation as for the classical solution. Stability and $L^{\infty}$ error estimates of approximate solutions for the corresponding schemes are obtained. using the extended Lax-Richtmyer equivalence theorem.

• Progress in Superconductivity
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• v.3 no.2
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• pp.172-177
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• 2002

Superconductive digital to analog converters (DAC) based on Josephson effect produce the voltage steps with high precision and good stability Therefore, they can be applied to obtain a very accurate ac voltage standard. In this paper, we made a simulation study of Rapid Single Flux Quantum (RSFQ) DAC. RSFQ DAC was composed of Non-destructive Head Out (NDRO) cells, T flip-flops, D flip-flops, Splitters, and Confluence Buffers. Confluence Buffer was used in resetting the DACs. We also obtained operating margins of the important circuit parameters in simulations.