• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.37 no.8
• /
• pp.528-533
• /
• 1988

The miniturization of a DC-to-DC converter in connection with the stability is investigated in this paper. As both the capacitance of the smoothing capacitor and the inductance of the reactor are reduced by rasing the switching frequency, it is known that the stability of the buck converter declines with the switching frequency but the buck-boost converter has a nearly uniform stability. Furthermore, that the buck-boost converter is suitable for the miniturization of circuit is cleared in the high frequency region above a certain switching frequency.

• 한국신재생에너지학회:학술대회논문집
• /
• 2006.06a
• /
• pp.551-554
• /
• 2006

An inverter system which consists of three bi-directional buck-boost converters, is proposed for motor driving. Three phase sinusoidal output voltages can be generated by utilizing three buck-boost converters. The advantage of this scheme is that it does not require a separate DC-DC converter for motor driving, i.e. inverter function is combined into the three DC-DC converters. This topology is suitable for inverters for hybrid or fuel cell vehicles where DC link voltage is subject to change depending upon charging status or output power. So the proposed system is capable of driving motor at high speed. The converter system is controlled by PI controller and simulation results done by MATLAB SIMULINK are provided.Ҙ?⨀ሉȀ̀㘰々K䍄乍?ጊ츀Ѐ㔹〻Ԁ䭃䑎䴀

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.50 no.2
• /
• pp.86-90
• /
• 2001

This paper presents a multi output converter system that controls, simultaneously, the separate buck converter and boost converter with the different specification by one digital controller using fuzzy algorithm. As two separate converters are regulated by only one DSP, it is possible to achieve the simple digital control circuit for regulating multi output DC-DC converter. Inference procedure of fuzzy controller is included. The control characteristics of each PWM DC-DC converter is validated by experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.411-414
• /
• 2011

This paper describes a tripple-mode DC-DC buck converter with DPSS Fucntion. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(80mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~80mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 97.02% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is $1465um{\times}895um$ including pads.

• Journal of Electrical Engineering and Technology
• /
• v.5 no.1
• /
• pp.171-178
• /
• 2010

Resonant parametric perturbation (RPP) method is an effective non-feedback method for controlling chaos. In this paper, the above method is applied for the current programmed buck-boost dc-dc converter which exhibits chaotic for wide parameter variations. The different possible operating regimes leading to chaotic operation of the current mode controlled buck-boost converter is discussed and the control of chaos by RPP method is demonstrated through computer simulations and experimental studies. The converter is stabilized to period 1 operation practically.

• Journal of the Korean Society of Industry Convergence
• /
• v.21 no.6
• /
• pp.265-271
• /
• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• Journal of Power Electronics
• /
• v.16 no.6
• /
• pp.2024-2034
• /
• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.12 no.5
• /
• pp.394-399
• /
• 2007

In this paper, we study on a novel Buck-Boost converter of high efficiency by soft switching method. The proposed Buck-Boost converter is applied to new soft switching method in restraint of increment of switching power loss in the conventional Buck-Boost converter. The soft switching circuit is designed to modification of a energy storage inductor and a snubber circuit used by the conventional converter, and then the proposed converter is simplified. The controlling switches of the proposed converter is operated with soft switching by a partial resonance behavior. The output voltage of the converter is regulated by PWM control technique. The discontinuous mode action of current flowing into inductor makes to simplify control method and control components. The proposed Buck-Boost converter is compared with the conventional converter. Some computer simulative results and experimental results are confirmed to the validity of the analytical results.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.8
• /
• pp.24-31
• /
• 2008

Power converters are becoming an essential block in modem mobile multimedia application. This paper presents a high performance DC-DC buck converter for mobile applications. Controller of DC-DC buck converter is designed by current-mode control method. An current-mode DC-DC converter is implemented in a standard $0.18{\mu}m$ CMOS process, and the overall die size was $1.2mm^2$. The peak efficiency was 86 % with a switching frequency of $1\sim1.5MHz$ and a maximum load current of 400mA.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.7A
• /
• pp.568-573
• /
• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.