• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.45-53
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• 2003

This paper describes a Unified Voltage Generator that merges the pumping capacitors of boosted voltage generator (VPP) and substrate voltage generator (VBB) for DRAM. This unified voltage generator simultaneously supplies VPP and VBB voltages by using one pumping capacitor and one oscillator. The proposed generator is realized by 0.14${\mu}{\textrm}{m}$DRAM process. The generator reduces the power consumption to 30%, the area of total generator to 40% and the area of pumping capacitor to 29.6%, and improves the pumping efficiency to 13.2% at 2.0V supply voltage. In addition, the generator adopts the charge recycling technique for precharging the pumping capacitor during the period of precharge, thatcan reduces the precharge current to 75%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.442-446
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• 2003

This paper proposes a new two-stage two-phase VPP charge pump configured in such a manner that body effect and the threshold voltage loss are eliminated. The newly proposed circuit is fabricated using 0.18um triple-well CMOS process and the measurement result shows that the VPP level tracks 3VDD when VDD is above the threshold voltage.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.530-533
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• 1998

In this paper, a new scheme of a boosted voltage generator (BVG) is designed for low powr DRAM's. The designed BVG can supply stable $V_{pp}$ using a new circuit operting method. This method controls charge pumping capability by switching the supply voltage and ring oscillator frequency of driving circuit, so the BVG can save area and reduce the powr dissipation during $V_{pp}$ maintaining period. The charge pumping circuit of the BVG suffers no $V_{T}$ loss and is to be applicable to low-voltage DRAM's. $V_{pp}$ level detecting circuit can detect constant value of $V_{pp}$ against temperature variation. The level of $V_{pp}$ varies -0.55%~0.098% during its maintaining period. Charge pumping circuit can make $V_{pp}$ level up to 2.95V with $V_{cc}$ =1.5V. The degecting level of $V_{pp}$ level detecting circuit changes -0.34% ~ 0.01% as temperature varies from -20 to 80.deg. C. The powr dissipation during V.$_{pp}$ maintaining period is 4.1mW.W.1mW.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.218-221
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• 2006

In this paper, a high-voltage generator with several mA draw output currents using LTPS-TFT technology is proposed. The new generator can be efficiently boosted about +18V output voltages with 5mA draw output currents and power efficiency ${\eta}$ is around 84% under the conditions of +5V power-supply voltage and 250kHz frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1155-1161
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• 2014

This paper proposes a start-up voltage generator for reducing the minimum input supply voltage of DC-DC boost converters to 250mV. The proposed start-up voltage generator boosts 250mV input voltage to over 500mV to charge the capacitor for starting the boost converter. After the boost converter operates initially with the supply voltage charged in the capacitor, it uses its boosted output voltage for the supply voltage. Therefore, after the start-up operation, the proposed DC-DC boost converter works as the same as the conventional one. The proposed start-up voltage generator reduces the threshold voltage of the transistors by adjusting the body voltage at a low input voltage. This causes the higher clock frequency and the larger current to a Dickson charge-pump for boosting the input voltage. The proposed start-up voltage generator was implemented with a $0.18{\mu}m$ CMOS process. Its clock frequency and output voltage were 34.5kHz and 522mV at 250mV input voltage, respectively.

• Journal of Electrical Engineering and Technology
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• v.10 no.6
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• pp.2297-2306
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• 2015

This paper presents the development of a system with a reverse matrix converter (RMC) for permanent magnet synchronous motor (PMSM) drive and its effective control method. The voltage transfer ratio of the general matrix converter is restricted to a maximum value of 0.866, which is not suitable for applications whose source voltages are lower than the load voltages. The proposed RMC topology can step up the voltage without any additional components in the conventional circuit. Its control method is different from traditional matrix converter’s one, thus this paper proposes control schemes of RMC by means of controlling both the generator and motor side currents with properly designed control loop. The converter can have sinusoidal input/output current waveforms in steady state condition as well as a boosted voltage. In this paper, a hardware system with an RMC for a PMSM drive system is described. The performance of the system was investigated through experiments

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.542-545
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• 1998

This paper presents a new reference voltage generator(RVG) for advanced DRAM's. The proposed RVG with three temperature coefficient is independent of temperature variation, and supply voltage. This is used to shorten leakage current using the boosted sense ground(BSG). This circuit is designed in a 0.8.mu.m nwell CMOS, double-polysilicon, double-metal technology. The simulation resutls in jindependent temperature and supply voltage. In hspice simulation results, temperature dependency of RVG is 130.mu.V/.deg. C and supply voltage dependency is .+-.0.91%, $V_{cc}$ =3.3V.+-. 0.5V.3.3V.+-. 0.5V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.776-780
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• 2007

In this paper, the charge pump circuit of a VPP generator for a low voltage DRAM is newly proposed. The proposed charge pump is a 2-stage cross coupled charge pump circuit. The charge transfer efficiency is improved, and Distributed Clock Inverter is located in each charge pump stage to reduce clock period so that the pumping current is increased. In addition, the precharge circuit is located at Gate node of charge transfer transistor to solve the problem which is that the Gate node is maintained high voltage because the boosted charge can't discharge, so device reliability is decreased. The simulation result is that pumping current, pumping efficiency and power efficiency is improved. The layout of the proposed VPP generator is designed using $0.18{\mu}m$ Triple-Well process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.520-523
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• 2016

This paper describes a DC-DC converter with MPPT control for thermoelectric energy harvesting. The designed circuit converts low voltage harvested from a thermoelectric generator into higher voltage for powering a load. A start-up circuit supplies VDD to a controller, and the controller turns on and off a NMOS switch of a main-boost converter. The converter supplies the boosted voltage to the load through the switch operation. Bulk-driven comparators can do the comparison under low voltage condition and are used for voltage regulation. Also, bulk-driven comparators raise system's efficiency. A peak conversion efficiency of 76% is achieved. The proposed circuit is designed in a 0.35um CMOS technology and its functionality has been verified through simulations. The designed chip occupies $933um{\times}769um$.