• Journal of The Korean Association of Information Education
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• v.13 no.3
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• pp.341-349
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• 2009

In this paper, we proposed an Electric Circuit manipulation method to identify easily results of Digital Logic Circuits. Using this method for computer science educations, we can feasibly instruct and understand principles of a Digital Logic Circuit which is a basis of real Digital systems. Furthermore, we developed an PBL-based education program for Digital Logic Circuit concept and Boolean Algebra concept by applying the proposed Electric Circuit manipulation method and by explaining real life Digital Instrument examples. The experimental results are analyzed in views of the problem-solving ability and suitability of allocating degrees of difficulties to the developed Digital Logic Circuit problems.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.29-34
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• 2010

This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.

• Journal of the Korea Computer Industry Society
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• v.8 no.4
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• pp.229-236
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• 2007

A factored form is a sum of products of sums of products, ..., of arbitrary depth. Factoring is the process of deriving a parenthesized form with the smallest number of literals from a two-level form of a logic expression. The factored form is not unique and described as either algebraic or Boolean. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpressions from given two-level logic expression and to extract divisor/quotient pairs. Then, we derive extended divisor/quotient pairs, where their quotients are not cube-free, from the generated divisor/quotients pairs. We generate quotient/quotient pairs from divisor/quotient pairs and extended divisor/quotient pairs. Using the pairs, we make a matrix to generate Boolean factored form based on a technique of rectangle covering.

• Journal of Applied and Pure Mathematics
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• v.5 no.1_2
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• pp.1-8
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• 2023

This study is on a Boolean B or Boolean lattice L in abstract algebra with closed binary operation *, complement and distributive properties. Both Binary operations and logic properties dominate this set. A lattice sheds light on binary operations and other algebraic structures. In particular, the construction of the elements of this L set from idempotent elements, our definition of k-order idempotent has led to the expanded definition of the definition of the lattice theory. In addition, a lattice offers clever solutions to vital problems in life with the concept of logic. The restriction on a lattice is clearly also limit such applications. The flexibility of logical theories adds even more vitality to practices. This is the main theme of the study. Therefore, the properties of the set elements resulting from the binary operation force the logic theory. According to the new definition given, some properties, lemmas and theorems of the lattice theory are examined. Examples of different situations are given.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.1-7
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• 2007

An MTJ element not only computes Boolean function but also stores the output result in itself. We can make the most use of magneto-logic's merits by employing the magneto-logic in substitution for the sequential logic as well as the combinational logic. This unique feature opens a new horizon for potential application of MTJ as a universal logic element. Magneto-logic circuits using MTJ elements are more integrative and non-volatile. This paper presents novel 3-bit magneto-logic up/down counters and presents simulation results based on the HSPICE macro-model of MTJ that we have developed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.844-850
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• 1988

In this paper, the implementation of optical parallel boolean logic gates using two Liquid Crystal TVs is described. Based on theory of polarization modulation, two Liquid Crystal TVs are arranged in tandem and parallel to perform optical logic operations. Experimental results of binary image using two Liquid Crystal TVs are presented.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.12-18
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• 1974

In this paper, we are concerned with the problem of generating fault-detection experiment for combinational logic networks with fan-out. We establish the lower limit on the necessary number of fault-section tests and show how such experiments can be obtained by considering inversion parity from the output to the point whore fan-out exilts on the networks. Boolean difference is used advantageously.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.8
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• pp.3715-3722
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• 2011

This paper presents a new Boolean extraction technique for logic synthesis. This method first calculates divisor/2-cube quotients, 2-cube quotient pairs, and 2-cube quotient matrices. Then we find candidates, which can be common sub-expressions, from 2-cube quotients and matrices. Next, candidate intersection provides the common sub-expressions for several logic expressions. Experimental results show the improvements in literal counts over the previous methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.1
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• pp.25-28
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• 1982

A method for finding the symbolic reliability expressision of a conbinational logic circuit is presented. The evaluation of the probabilities of the outputs can be symbolically evaluated by the Boolean operation named sharp operation, provided that every input of such a circuit can be treated as random variables with values set(0, 1) and the output of a circuit can be represented by a Boolean sum of produt expression.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.1
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• pp.25-35
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• 2013

Automatically deriving only individual don't-care minterms that can effectively reduce a Boolean logic expressions are being investigated. Don't-care conditions play an important role in optimizing logic design. The type of unknown don't-care minterms that can always reduce the number of product terms in Boolean expression are referred as single hypothetical don't-care (S-HDC) minterms. This paper describes the Quasi Quine-McCluskey method that systematically derives S-HDC minterms. For the most part, this method is similar to the original Quine-McCluskey method in deriving the prime implicants. However, the Quasi Quine-McCluskey method further derives S-HDC minterms by applying so-called a combinatorial comparison operation. Upon completion of the procedure, the designer can review generated S-HDC minterms to test its appropriateness for a particular application.