Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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New Parity-Preserving Reversible Logic Gate

새로운 패리티 보존형 가역 논리게이트

  • Kim, Sung-Kyoung (Graduate School of Information Management and Security, Korea University) ;
  • Kim, Tae-Hyun (The Attached Institute of ETRI) ;
  • Han, Dong-Guk (Department of Mathematics, Kookmin University) ;
  • Hong, Seok-Hie (Graduate School of Information Management and Security, Korea University)
  • 김성경 (고려대학교 정보경영공학전문대학원) ;
  • 김태현 (한국전자통신연구원(ETRI) 부설연구소) ;
  • 한동국 (국민대학교 수학과) ;
  • 홍석희 (고려대학교 정보경영공학전문대학원)
  • Published : 2010.01.25
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Abstract

This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.

본 논문에서는 새로운 패리티 보존형 가역 논리게이트를 제안한다. 패리티 보존형 가역 논리게이트는 입력 값과 출력 값의 패리티가 같은 가역 논리게이트를 의미한다. 최근 가역 논리 게이트가 저전력 CMOS 디자인, 양자 컴퓨팅 그리고 나노 테크놀로지와 같은 분야에서 전력을 효율적으로 사용하는 방법임을 알려졌다. 그리고 패리티 체크(parity-checking)는 디지털 시스템에서 오류 주입을 확인 하는 대표적인 방법 중 하나이다. 제안하는 새로운 패리티 보존형 가역 논리게이트는 모든 boolean 함수를 구성할 수 있고, 기존의 오류 확인 boolean 함수보다 가역 논리게이트 수, garbage-output의 수 그리고 하드웨어 연산량에서 효율적으로 구성할 수 있다.

Keywords

References

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