• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.53-57
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• 2013

Although the lowering of Ag content in Sn-3.0Ag-0.5Cu is known to improve the mechanical shock reliability of the solder joint, it is also known to be detrimental to the solderbility. In this study, the quaternary alloying effect of In and the minor alloying effects of Mn and Pd on the solderability, thermal cycling and mechanical shock reliabilities of the low Ag content Sn-1.2Ag-0.7Cu solder were investigated using board-level BGA packages. The solderability of Sn-1.2Ag-0.7Cu-0.4In was proved to be comparable to that of Sn-3.0Ag-0.5Cu but its thermal cycling reliability was inferior to that of Sn-3.0Ag-0.5Cu. While the 0.03 wt% Pd addition to the Sn-1.2Ag-0.7Cu-0.4In decreased the solderability and reliabilities of solder joint, the 0.1 wt% Mn addition was proved to be beneficial especially for the mechanical shock reliability compared to those of Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu compositions. It was considered to be due that the Mn addition decreased the Young's modulus of low Ag content Pb-free solders.

• Journal of Welding and Joining
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• v.21 no.4
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• pp.25-30
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• 2003

There have been many researches for small scale packages such as CSP, BGA, and Flipchip. Underfill encapsulant technology is one of the latest assembly technologies. The underfill encapsulant could enhance the reliability of the packages by flowing into the gap between die and substrate. In this paper, the effects of underfill packages by both aspects of thermal and mechanical reliabilities are studied. Especially, it is focused to value board-level reliability whether by the underfill is applied or not. First of all, The predicted thermal fatigue lifes of underfilled and no underfilled $\mu$ BGA solder joints are performed by Coffin-Manson's equation and FEA program, ANSYS(version 5.62). Also, the thermal fatigue lifes of $\mu$ BGA solder joints are experimented by thermal cycle test during the temperature, 218K to 423k. Consequently, both experimental and numerical study show that $\mu$ BGA with underfill has over ten times better fatigue lift than $\mu$ BGA without underfill.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.9
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• pp.1379-1384
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• 2017

To guarantee safety and reliability, RAMS(Reliability Availability Maintainability and Safety) activity for a communication software in train communication network is studied. In this paper, preliminary hazard analysis in RAMS activities is studied for the communication software. Preliminary hazard analysis is done through library for communication software that the specification is defined by IEC 61375. The hazards are defined, then causes and consequence for each hazard are defined. The total 36 preliminary hazards are classified. For high severity hazards are changed to acceptable level by upgrading of system requirement specification.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.77-86
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• 2008

The reliability of leaded and lead-free solders of BGA type packages on a printed circuit board was investigated by employing the standard drop test and 4-point bending test. Tested solder joints were examined by optical microscopy to identify associated failure mode. Three-dimensional finite element analysis(FEM) with ANSYS Workbench v.11 was carried out to understand the mechanical behavior of solder joints under the influence of bending or drop impact. The results of numerical analysis are in good agreement with those obtained by experiments. Packages in the center of the PCB experienced higher stress than those in the perimeter of the PCB. The solder joints located in the outermost comer of the package suffered from higher stress than those located in center region. In both drop and bending impact tests, the lead-free solder showed better performances than the leaded solders. The numerical analysis results indicated that stress and strain behavior of solder joint were dependent on various effective parameters.

• Journal of Arbitration Studies
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• v.7 no.1
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• pp.411-446
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• 1997

This paper reports the results of an experimental companson of the winning rates in arbitral awards between the Korean Commercial Arbitration Board and the Japan Commercial Arbitration Association, and analyzed the comparative advantages of KCAB in international arbitration compared with ICC. There are so many factors to analyze the level of internationalizaton and competitiveness in the arbitration. From the recent lituratures, arbitration experts reported and debated tremendous elements which is vital to have a competition in the international arbitration market. Arbitration factors such as fairness, reliability, awareness, extension, enforcement, inexpensiveness, closed and expedited proceedings, arbitrators, expert knowledge, service, arbitral award, etc. are very important to appraise the level of the globalization and competitiveness of arbitration organizations Using these factors, I appraised current level of the globalization and competitiveness of the Korean Commercial Arbitration Board, unique arbitration organization in South Korea. Next, we are able to compare the level of fairness using the concept of 'winning rate' All over the world, only several arbitration organizations published and opened their own arbitral awards even In anonymity. The Japanese arbitration institutions published it regularly as well as the Korean When compared with these two institutions' "winning rates". there is similiar tendency in favor of domestic corporations That is to say, the winning rates in domestic arbitration cases are greater than those in international arbitration cases. This embarks an implication of unequality, a part of unfairness, in these two countries' arbitration. Finally, an analysis was conducted between the statistics of KCAB and ICC, especially to the focus on the number of arbitration cases, arbitration tribunals, arbitration places, parties' nationalities. the types of contents, the amount of arbitration, arbitration costs. There are two meanings to keep in mind for advancement of Korean arbitration. One is to establish new strategy specializing in small amount arbitration less than US$200,000. The other is to rearrange the panel of arbitration, especially in increasing field of arbitration cases such as the disputes of license, technology transfer, patent, etc.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.10
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2217-2220
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• 2007

In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.47-56
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• 2015

In this paper, the Thermal behavior and reliability characteristics of carbon CCL (Copper Claded Layer), which can be used as the core of HDI (High Density Interconnection) PCB (Printed Circuit Board) are evaluated through experiments and numerical analysis using CAE (Computer Aided Engineering) software. For the characterization of the carbon CCL, it is compared with the conventional FR-4 core and Heavy Cu core. From research results, the deformation amount of the flexure strength of PCB is the highest with pitch grade carbon and thermal behavior of PCB is lowest as temperature increases. In addition, TC (Thermal Cycling), LLTS (Liquid-to-Liquid Thermal Shock) and Humidity tests have been applied in the PCB with carbon core and the reliability of PCB with carbon core is confirmed through reliability tests. Also, possibility of uneven surface of the via hole and wear of the drill bit due to the carbon fibers are analyzed. surface of the via hole is uniform, the surface of the drill bit is smooth. Therefore, it is proved that the carbon CCL has the drilling workability of the same level as conventional core material.