• Title/Summary/Keyword: Bit node

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Performance Relation Analysis of CLR, Buffer Capacity and Delay Time in the ATM Access Node (ATM 접속노드에서 셀 손실율과 버퍼용량 및 지연시간의 상관관계 분석)

  • 이하철;이병섭
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.10C
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    • pp.945-950
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    • 2002
  • In this paper the performance evaluations on Asynchronous Transfer Mode(ATM) access node are performed in the ATM access network which consists of access node and channel. The performance factors of access node are Cell Loss Ratio(CLR), buffer capacity and delay time. Both the ATM cell-scale queueing model and burst-scale queueing model are considered as the traffic model of access node for various traffic types such as Constant Bit Rate(CBR), Variable Bit Rate(VBR) and random traffic in the ATM access networks. Based on these situations, the relation of CLR, buffer capacity and delay time is analyzed in the ATM access node.

Bit-Map Based Hybrid Fast IP Lookup Technique (비트-맵 기반의 혼합형 고속 IP 검색 기법)

  • Oh Seung-Hyun
    • Journal of Korea Multimedia Society
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    • v.9 no.2
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    • pp.244-254
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    • 2006
  • This paper presents an efficient hybrid technique to compact the trie indexing the huge forward table small enough to be stored into cache for speeding up IP lookup. It combines two techniques, an encoding scheme called bit-map and a controlled-prefix expanding scheme to replace slow memory search with few fast-memory accesses and computations. For compaction, the bit-map represents each index and child pointer with one bit respectively. For example, when one node denotes n bits, the bit-map gives a high compression rate by consumes $2^{n-1}$ bits for $2^n$ index and child link pointers branched out of the node. The controlled-prefix expanding scheme determines the number of address bits represented by all root node of each trie's level. At this time, controlled-prefix scheme use a dynamic programming technique to get a smallest trie memory size with given number of trie's level. This paper proposes standard that can choose suitable trie structure depending on memory size of system and the required IP lookup speed presenting optimal memory size and the lookup speed according to trie level number.

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Bit-level Array Structure Representation of Weight and Optimization Method to Design Pre-Trained Neural Network (학습된 신경망 설계를 위한 가중치의 비트-레벨 어레이 구조 표현과 최적화 방법)

  • Lim, Guk-Chan;Kwak, Woo-Young;Lee, Hyun-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.9
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    • pp.37-44
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    • 2002
  • This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

Design Methodology of LDPC Codes based on Partial Parallel Algorithm (부분병렬 알고리즘 기반의 LDPC 부호 구현 방안)

  • Jung, Ji-Won
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.4
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    • pp.278-285
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    • 2011
  • This paper makes an analysis of the encoding structure and the decoding algorithm proposed by the DVB-S2 specification. The methods of implementing the LDPC decoder are fully serial decoder, the partially parallel decoder and the fully parallel decoder. The partial parallel scheme is the efficient selection to achieve appropriate trade-offs between hardware complexity and decoding speed. Therefore, this paper proposed an efficient memory structure for check node update block, bit node update block, and LLR memory.

Distributed beamforming with one-bit feedback and clustering for multi-node wireless energy transfer

  • Lee, Jonghyeok;Hwang, SeongJun;Hong, Yong-gi;Park, Jaehyun;Byun, Woo-Jin
    • ETRI Journal
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    • v.43 no.2
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    • pp.221-231
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    • 2021
  • To resolve energy depletion issues in massive Internet of Things sensor networks, we developed a set of distributed energy beamforming methods with one-bit feedback and clustering for multi-node wireless energy transfer, where multiple singleantenna distributed energy transmitters (Txs) transfer their energy to multiple nodes wirelessly. Unlike previous works focusing on distributed information beamforming using a single energy receiver (Rx) node, we developed a distributed energy beamforming method for multiple Rx nodes. Additionally, we propose two clustering methods in which each Tx node chooses a suitable Rx node. Furthermore, we propose a fast distributed beamforming method based on Tx sub-clustering. Through computer simulations, we demonstrate that the proposed distributed beamforming method makes it possible to transfer wireless energy to massive numbers of sensors effectively and rapidly with small implementation complexity. We also analyze the energy harvesting outage probability of the proposed beamforming method, which provides insights into the design of wireless energy transfer networks with distributed beamforming.

Multi-Stride Decision Trie for IP Address Lookup

  • Lee, Jungwon;Lim, Hyesook
    • IEIE Transactions on Smart Processing and Computing
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    • v.5 no.5
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    • pp.331-336
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    • 2016
  • Multi-bit tries have been proposed to improve the search performance of a binary trie by providing flexibility in stride values, which identify the number of bits examined at a time. However, constructing a variable-stride multi-bit trie is challenging since it is not easy to determine a proper stride value that satisfies the required performance at each node. The aim of this paper is to identify several desired characteristics of a trie for IP address lookup problems, and to propose a multi-stride decision trie that has these characteristics. Simulation results using actual routing sets with about 30,000 to 220,000 prefixes show that the proposed multi-stride decision trie has the desired characteristics and achieves IP address lookup using 33% to 47% of the 2-bit trie in the average number of node accesses, while requiring a smaller amount of memory.

A Study on the Performance Improvement of Message Transmission over MVB(Multifunction Vehicle Bus)

  • Choi, Myung-Ho;Park, Jae-Hyun
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2198-2202
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    • 2003
  • The data transmission of MVB(Multifunction Vehicle Bus) of TCN(Train Network Communication) is divided into the periodic transmission phase and the sporadic transmission phase. TCN standard defines the event-polling method for the message transfer in the sporadic phase. However, since the event-polling method does not use pre-scheduling to the priority of the messages to be transmitted, it is inefficient for the real-time systems. To schedule message transmission, a master node should know the priority of message to be transmitted by a slave node prior to the scheduling the sporadic phase, but the existing TCN standard does not support any protocol for this. This paper proposes the slave frame bit-stuffing algorithm, with which a master node gets the necessary information for transmission scheduling and includes the simulation results of the event-polling method and the proposed algorithm.

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A Study of Jitter Reduction for SDH Transmission System using Sigma-Delta Modulation

  • Han, Wook;Chang, Jin-Hyeon;Kim, Yung-Kwon
    • Journal of IKEEE
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    • v.3 no.1 s.4
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    • pp.126-132
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    • 1999
  • The SDH (Synchronous Digital Hierarchy) has been rapidly acknowledged as a world wide transmission standard replacing the existing PDH infrastructure. A bit stuffing is used for synchronization between a PDH signal and a SDH node, and a pointer justification is used for synchronization between one SDH node and the other SDH node. During above processes - a bit stuffing and a pointer processing -, a stuffing jitter and a pointer Jitter are produced and the generated jitter can cause transmission error. In this study, a stuffing jitter and a pointer jitter are modeled and analyzed. A Sigma-Delta modulation is described and an advanced jitter reduction technique using a Sigma-Delta modulation technique in the Synchronizer, Pointer Processor and Desynchronizer is provided.

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Performance Improvement of Message Transmission over TCN(Train Communication Network) (TCN을 통한 메시지 전송 능력 향상에 관한 연구)

  • Cho Myung-ho;Moon Chong-chun;Park Jaehyun
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.10
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    • pp.720-726
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    • 2004
  • The data transmission over MVB(Multifunction Vehicle Bus) of TCN(Train Communication Network) is divided into the periodic transmission phase and the sporadic transmission phase. TCN standard recommends the event-polling method as the message transfer in the sporadic phase. However, since the event-polling method does not use pre-scheduling to the priority of the messages, it is inefficient for the real-time systems. To schedule message transmission, a master node should know the priority of message to be transmitted by a slave node prior to the sporadic phase, but the existing TCN standard does not support any protocol for this. This paper proposes the slave frame bit-stuffing algorithm, with which a master node gets the necessary information for scheduling and includes the simulation results of the event-polling method and the proposed algorithm.

The Relation of CLR and Blocking Probability for CBR Traffic in the Wireless ATM Access Network

  • Lee, Ha-Cheol;Lee, Byung-Seub
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.11C
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    • pp.1158-1163
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    • 2002
  • In this paper it is focused on the relation between CLR (Cell Loss Ratio) and blocking probability, GoS(Grade of Services) parameters in the wireless ATM (Asynchronous Transfer Mode) access network which consists of access node and wireless channel. Traffic model of wireless ATM access network is based on the cell scale, burst scale and call connection level. The CLR equation due to buffer overflow for wireless access node is derived for CBR (Constant Bit Rate) traffic. The CLR equation due to random bit errors and burst errors for wireless channel is derived. Using the CLR equation for both access node and wireless channel, the CLR equation of wireless ATM access network is derived. The relation between access network CLR and blocking probability is analyzed for CBR traffic.