• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.26-35
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• 1997

This paper proposes a multi-bit $\Sigma\Delta$ modulator arcitecture which eliminates signal clipping problem. To avoid signal clipping, the output values of intgrators are monitored and modified by a reference value. This oepration is recorded as a digital code to restore actual signal value. Due to the digital code, the substraction of feedback value from the multi-bit quantizer can be calculated by a digital adder and this simplifies dAC operation making the accurate DAC of conventional multi-bit $\Sigma\Delta$ modulator scheme unnecessary. These features make N-th modulator can be implemented by sharing an integrator among N stages to decrease the required chip area. As an experimental example, a 4th order .sum..DELTA. modulator with oversampling ratio of 64 was simulated to show over 130 DB SNR at rail-to-rail input sinusoidal signal.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.1
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• pp.41-48
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• 1998

This paper proposes a new addition algorithm to improve the addition speed which is one of the important factors for data path functions. We have designed a fast 64-bit adder utilizing al dynamic chain architecture based on the proposed Sum-Selector Generation (SSG) algorithm. Proposed adder is designed with pass-transistor logicto achieve a high speed operation in low voltage circumstance. Realized 64-bit adder with 0.8.mu.m CMOS double-metal process technology has been fully tested. it operates at 185 MHz with 5.0V and chip area occupies 3.66mm$^{2}$. It is also demonstrated that designed adder operates even at 2.0V power supply condition.

• Progress in Superconductivity
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• v.5 no.1
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2750-2767
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• 1996

In this papr, a new lossless compression method is presented based on the Binary Adaptive Arithmetic Coder(BAAC). A simple unbalanced binary tree is created by recursively dividing the BAAC unit interval into two probability sub-inervals. On the tree the More Probable Predicted Value(MPPV) and Less Probable Predicated Value(LPPV) estimated by local statistics of the image pixels are arranged in decreasing order. The BAAC or Huffman coder is thus applied to the branches of the tree. The proposed method allows the coder be directly applied to the full bit-plane medical image without a decomposition of the full bit-planes into a series of binary bit-planes. The use of the full bit model template improves the compresion ratio. In addition, a fast computation for adjusting the interval is possible since a simple arithmetic operation based on probability interval estimation state machine is used for interval sub-division within the BAAC unit interval.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.363-367
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• 1999

In this paper, a novel 108-bit conditional sum adder(CSA) with Energy Economized Pass-transistor Logic(EEPL) is proposed. A new architecture is adopted, in order to obtain a high speed operation, which is composed of seven modularized 16-bit CMS's and two separated carry generation block. Further a design technique based on EEPL is proposed to reduce the power consumption. With 0.65${\mu}{\textrm}{m}$ single poly, triple metal, 3.3V CMOS process, its operating speed is about 4.95㎱ and the power consumption is reduced in comparison with that of the conventional adder.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.1-8
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• 1980

A distributed control system is designed and imp, fomented to control various pert pherals of a playback-type industrial robot :or synchronized work motion. The distn buted control system conslists of a 16- bit Mini-computer and several 8bit Micro-computers. In the paper, the struttuie of the control system, the software requirements for system operation as well as the hierarchical computer network for interfacing module computers and the Mini - computer are briefly described. and practical difficulties including including interfacing problem ate discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.3-5
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• 2000

1.8V,4Gb DDR SDRAM설계 및 제작을 수행하였다. DRAM동작 시 발생하는 Bit Line간 CouplingNoise를 보상하기 위한 Twisted Open Bit Line 구조를 제안하였다. Low Voltage Operation으로 인한 Bit Line Sense Amplifier 의 동작 저하를 보상하기 위한 BL S/A Pre-Sensing 방식 및 Reference Bit Line Voltage Calibration 구조를 제안하였다. Chip면적 증가로 인한 동작속도 감소의 보상을 위해 Repeater Driver 구조를 Core 및 Periphery Circuit에 적용하여 동작 대비 Chip 면적의 증가를 최소화 하도록 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.26-27
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• 2006

To develop tera-bit level SONOS flash memories, SONOS unit memory and 64 bit flash arrays are fabricated. The unit cells have both channel length and width of 30nm. The NAND & NOR arrays are fabricated on SOI wafer and patterned by E-beam. The unit cells represent good write/erase characteristics and reliability characteristics. SSL-NOR array have normal write/erase operation. These researches are leading the realization of Tera-bit level non-volatile nano flash memory.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.404-405
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• 2019

본 논문에서는 PMSM(Permanent magnet synchronous motor)의 MTPA(Maximum Torque Per Ampere) 운전을 고려한 V/f 제어 시 안정화 기법에 대해 제안한다. PMSM은 V/f 제어 시 부하 변동에 따라 탈조할 가능성이 있다. 제안된 기법은 안정도 개선을 위해 추정된 q축 전류를 이용하여 부하 변동정보를 얻고 이를 바탕으로 고정자 주파수를 변동하여 회전자 속도가 동기속도를 유지할 수 있는 안정화 기법을 적용하였다. 제안된 안정화 기법으로 저속 영역부터 약자속 영역까지 부하변동에도 안정적인 운전이 가능하도록 하였다. 1kW SPMSM의 모의실험을 통하여 제안된 기법의 효용성을 검증하였다.