Sum-selector generation algorithm based 64-bit adder design

SUM 선택신호 발생 방식을 이용한 64-bit 가산기의 설계

This paper proposes a new addition algorithm to improve the addition speed which is one of the important factors for data path functions. We have designed a fast 64-bit adder utilizing al dynamic chain architecture based on the proposed Sum-Selector Generation (SSG) algorithm. Proposed adder is designed with pass-transistor logicto achieve a high speed operation in low voltage circumstance. Realized 64-bit adder with 0.8.mu.m CMOS double-metal process technology has been fully tested. it operates at 185 MHz with 5.0V and chip area occupies 3.66mm$^{2}$. It is also demonstrated that designed adder operates even at 2.0V power supply condition.