• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.2 s.314
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• pp.39-45
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• 2007

This paper presents a novel scheme that quickly searches for the sweet spot of multiple array antennas, and locks on to it for high-speed millimeter wavelength transmissions, when communications to another antenna array are disconnected. The proposed method utilizes a modified genetic algorithm, which selects a superior initial group through preprocessing in order to solve the local solution in agenetic algorithm. TDD (Time Division Duplex) is utilized as the transfer method and data controller for the antenna. Once the initial communication is completed for the specific number of individuals, no longer antenna's data will be transmitted until each station processes GA in order to produce the next generation. After reproduction, individuals of the next generation become the data, and communication between each station is made again. Simulation results of 1:1, 1:2, 1:5 array antennas confirmed the efficiency of the proposed method. The 16bit split is 8bit, but it has similar performance as 16bit gene.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• International journal of advanced smart convergence
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• v.11 no.4
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.603-604
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• 2008

This paper implemented The LED illuminance control IP based on 8bit RISC Processor. 8bit RISC Processor designed hardware interrupts, an interface for serial communications, a timer system with compare-capture-reload resources and a watchdog timer. LED Array consists of Red, Green, Blue, White and Warm White. The illuminance control IP is used to LED Board control with 8bit data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.9-14
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• 2009

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.3 s.234
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• pp.418-424
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• 2005

We present the design, fabrication and experimental results of 4-bit digital microinjectors, whose ejected droplet volumes are adjusted by the digital operation of a 4-bit microheater array. We design the reference microinjectors as well as its comparative test structures. In the fabrication process, we use a five-mask micromachining process and the total chip size of the fabricated microinjector is $7,640{\mu}m{\times}5,260{\mu}m.$ We measure the ejected droplet volumes and velocities, which are adjusted from $12.1{\pm}1.0~55.6{\pm}14.7pl\;and\;2.3{\pm}0.1~15.7{\pm}0.8m/s.$ respectively, depending on the 15 possible combinations of 4-bit microheater array. We also experimentally characterize the effect of geometric variation including the microheater size, inter-microheater gap, microchannel width and sequential operation of microheater array on the ejected droplet volume and velocity. Among these parameters, we find that the microheater size is the most dominant parameter affected to the ejected droplet volumes and velocities. Thus, the present microinjector has a potential for application to the high-resolution inkjet printers with multiple gray levels or high-precision fluid injectors with variable volume control.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.1-6
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• 2010

We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.

• ETRI Journal
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• v.46 no.4
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• pp.708-715
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• 2024

We propose a 10-GHz 2 × 2 phased-array radio frequency (RF) receiver with an 8-bit linear phase and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology. An 8 × 8 phased-array receiver module is implemented using 16 2 × 2 RF phased-array integrated circuits. The receiver chip has four single-to-differential low-noise amplifier and gain-controlled phase-shifter (GCPS) channels, four channel combiners, and a 50-Ω driver. Using a novel complementary bias technique in a phase-shifting core circuit and an equivalent resistance-controlled resistor-inductor-capacitor load, the GCPS based on vector-sum structure increases the phase resolution with weighting-factor controllability, enabling the vector-sum phase-shifting circuit to require a low current and small area due to its small 1.2-V supply. The 2 × 2 phased-array RF receiver chip has a power gain of 21 dB per channel and a 5.7-dB maximum single-channel noise-figure gain. The chip shows 8-bit phase states with a 2.39° root mean-square (RMS) phase error and a 0.4-dB RMS gain error with a 15-dB gain control range for a 2.5° RMS phase error over the 10 to10.5-GHz band.