• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.11
• /
• pp.1143-1153
• /
• 1991

In this paper, we proposed a new ATM switch structure which is based on the GAMMA network, proving multipath between an input and an output port. The size of the proposed new ATM switch will be smaller than the switches based on the BANYAN network, which includes the Sorting network to resolve the blocking in the switch fabric. Also, the validity and the utility of the proposed switch structure is verified through a simulation method.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.12
• /
• pp.8-16
• /
• 1998

In this paper, we propose the non-blocking pattern generator(NBPG) for banyan ATM switches and evaluate the performance by simulation. The proposed NBPG first classifies input cells into two groups. the conflict intended cells are assigned to their new non-blocking input addresses by the conflict table. Simulation results show that the NBPG generates non-blocking address patterns with minimal changes.

• Journal of Korean Institute of Industrial Engineers
• /
• v.19 no.1
• /
• pp.47-59
• /
• 1993

Recently, Broadband ISDN(B-ISDN) has received increased attention as a communication architecture which can support multimedia applications. Also, Asynchronous Transfer Mode(ATM) is considered as a promising technique to transfer and switch various kinds of media, such as telephone speech, data and motion video. Comparisons among a variety of ATM switching systems which have already been proposed will provide quite useful information for the new ATM switching system design. To facilitate the comparison, we introduce the design requirements and classification criteria for the ATM switch, and propose a performance analysis model for the Banyan network which is the basic switching fabric of most multi-stage ATM switching systems. The model is based on the standard discrete-time Markov chain analysis and can be conveniently used for extensive Banyan network analysis. The computational results are also presented.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.25 no.1
• /
• pp.13-18
• /
• 2011

• Journal of KIISE:Information Networking
• /
• v.28 no.3
• /
• pp.447-453
• /
• 2001

In this paper, we consider the scheduling of SE(switching element)-disjoint multicasting in photonic Banyan-type switching networks constructed with directional couplers. This ensures that at most, one connection holds each SE in a given time thus, neither crosstalk nor blocking will arise in the network. Such multicasting usually takes several routing rounds hence, it is desirable to keep the number of rounds(i.e., scheduling length) to a minimum. We first present the necessary and sufficient condition for connections to pass through a common SE(i.e., make crosstalk) in the photonic Banyan-type networks capable of supporting one-to-many connections. With definition of uniquely splitting a multicast connection into distinct subconnections, the crosstalk relationship of a set of connections is represented by a graph model. In order to analyze the worst case crosstalk we characterize the upper bound on the degree of the graph. The successor paper(Part II)[14] is devoted to the scheduling algorithm and the upper bound on the scheduling length. Comparison with related results is made in detail.

• Journal of Internet Computing and Services
• /
• v.3 no.3
• /
• pp.87-93
• /
• 2002

A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max＋plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.

• The Journal of the Korea Contents Association
• /
• v.4 no.4
• /
• pp.189-196
• /
• 2004

Most of the recent researches for ATM switches have been based on multistage interconnection network known as regularity and self-routing property. These networks can switch packets simultaneously and in parallel. However, they are blocking networks in the sense that packet is capable of collision with each other Mainly Banyan network have been used for structure. There are several ways to reduce the blocking or to increase the throughput of banyan-type switches: increasing the internal link speeds, placing buffers in each switching node, using multiple path, distributing the load evenly in front of the banyan network and so on. Therefore, this paper proposes the use of recirculating shuffle-exchange network to reduce the blocking and to improve hardware complexity. This structures are recirculating shuffle-exchange network as simplified in hardware complexity and Rank network with tree structure which send only a packet with highest priority to the next network, and recirculate the others to the previous network. after it decides priority number on the Packets transferred to the same destination, The transferred Packets into banyan network use the function of self routing through decomposition and composition algorithm and all they arrive at final destinations. To analyze throughput, waiting time and packet loss ratio according to the size of buffer, the probabilities are modeled by a binomial distribution of packet arrival. If it is 50 percentage of load, the size of buffer is more than 15. It means the acceptable packet loss ratio. Therefore, this paper simplify the hardware complexity as use of recirculating shuffle-exchange network instead of bitonic sorter.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.9
• /
• pp.73-80
• /
• 2004

In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.6
• /
• pp.1137-1147
• /
• 1997

I propose a RZETA network consisted of switching elements(SEs) that have regular links and alternate links. A modified Zeta nework used for the RZETA network's regular links and a MIN used for its alternate links are generated using the graph theory. The RZETA network is driven from merging the formaer and latter MINs. A necessary and sufficient condition for modified Zeta network to be a nonblocking network is also presented. This condition is a ufficient condition for RZETA network with a faulty link or a faulty SE to be nonblocked. Performance of the RZETA network is analyzed by modification of the model of 2-dilated Banyan network and its performance is compared with existing redundant path networks, when packet arrival rate of each source is 1.

• Proceedings of the KAIS Fall Conference
• /
• 2002.11a
• /
• pp.209-211
• /
• 2002

본 연구에서는 비교적 하드웨어의 복잡성보다는 효율적인 Routing 알고리즘을 통하여 스위칭 네트워크의 성능을 향상시킬 수 있는 Sort-Banyan을 기본으로 한 스위칭 구조를 근간으로 하여 하드웨어 구조의 개선과 그에 맞는 최적의 Routing 알고리즘을 개발하고자 한다. 따라서 고속 통신망의 스위치 네트워크를 구현하기 위해 두 단계의 패킷 분배 결정 알고리즘을 구성하고 그에 따라 분배를 결정하여 패킷이 전송될 때 출력 단에서 충돌이 발생하지 않도록 사전에 선택적으로 전송함으로서 패킷의 손실을 방지하는 패킷 스위치 네트워크를 제안한다.