• Journal of Welding and Joining
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• 제17권6호
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• pp.78-83
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• 1999

Solder joint is the weakest part which connects in mechanically and electronically between package body and PCB(Printed Circuit Board). Recently, the reliability of solder joint become the most critical issue in surface mounted technology. The solder joint interconnection between plastic package and PCB is susceptible to shear stress during thermal storage due to the mismatch in coefficient of thermal expansion between plastic package and PCB. A general computational approach to determine the effect of solder joint shape on the fatigue life presented. The thermal fatigue life was estimated from the engelmaier equation which was obtained from the temperature cycling loading($-65^{\circ}C$ to $150^{\circ}C$). As result of the simulation, TSOP structure has the shortest thermal fatigue life and the same structure Copper lead has 2.5 times as much fatigue life as Alloy 42 lead. In BGA structure, fatigue life time extended 80 times when underfill material exists.

• 마이크로전자및패키징학회지
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• 제20권3호
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package)는 가전제품, 자동차, 모바일, 데스크톱 PC등을 위한 저렴한 비용의 패키지로, 리드 프레임을 사용하는 IC패키지이다. TSOP는 BGA와 flip-chip CSP에 비해 우수한 성능은 아니지만, 저렴한 가격 때문에 많은 분야에 널리 사용되고 있습니다. 그러나, TSOP 패키지에서 몰딩공정 할 때 리드프레임의 열적 처짐 현상이 빈번하게 일어나고, 반도체 다이와 패드 사이의 Au 와이어 떨어짐 현상이 이슈가 되고 있다. 이러한 문제점을 해결하기 위해서는 리드프레임의 구조를 개선하고 낮은 CTE를 갖는 재료로 대체해야 한다. 본 연구에서는 열적 안정성을 갖도록 리드프레임 구조 개선을 위해 수치해석적 방법으로 진행하였다. TSOP 패키지에서 리드프레임의 열적 처짐은 반도체와 다이 사이의 거리(198 um~366 um)에서 안티-디플렉션의 위치에 따라 시뮬레이션을 진행하였다. 안티-디플렉션으로 TSOP 패키지의 열적 처짐은 확실히 개선되는 것을 확인 했다. 안티-디플렉션의 위치가 inside(198 um)일 때 30.738 um 처짐을 보였다. 이러한 결과는 리드프레임의 열적 팽창을 제한하는데 안티-디플렉션이 기여하고 있기 때문이다. 그러므로 리드프레임 패키지에 안티-디플렉션을 적용하게 되면 낮은 CTE를 갖는 재료로 대체하지 않아도 열적 처짐을 향상시킬 수 있음을 기대할 수 있다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.80-80
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• 2000

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2007년도 추계학술대회 논문집
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• pp.35-35
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• 2007

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.98.1-98
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• 1998

• 한국전기전자재료학회논문지
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• 제17권6호
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• pp.575-579
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• 2004

Package reliability test was conducted to investigate the effect of solder paste composition at BGA Package. It was found that the shape and size of the phase form are affected by the processing parameters. The material have used to fill in the via was Sn/36Pb/2Ag and Sn/0.75Cu type solder paste. Sn/36Pb/2Ag and Sn/0.75Cu paste were fabricated on Tape-BGA substrates by screen printing process, and via ball mount data were characterized with variations of dwell time of 85 seconds at reflow peak temperature at 22$0^{\circ}C$ or 24$0^{\circ}C$. The test condition was MRT 30 $^{\circ}C$/60 %RH/96 HR. Failures formed of a ball-off in solder paste process were observed by using a Optical Microscope and SEM(Scanning Electron Microscope). It was concluded that intermetallic layer growth played important roles in increasing solder fatigue strength for addition of Ag composition. The degradation of shear strength of solder composition is discussed.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2002년도 Proceedings of the International Welding/Joining Conference-Korea
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• pp.463-468
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• 2002

This study investigates the variations of shear force, displacement, and fracture surface with the shear speed and the number of reflows. The experimental data of shear tests indicate that the shear force increases as increasing the number of reflows and the shear speed due to the formation of a kind of intermetallic compound, Ni$_3$Sn$_4$, on Au/Ni/Cu pad, and the work-hardening. However, general trends show that the shear force decreases due to increasing the thickness of the intermetallic compound over 4x reflow. It is observed that the intermetallic compound which is formed between solder and pad increases according to increasing the number of reflows, and the growth rate of the intermetallic compound at central region on the interface is faster than one at edge part. The general tendencies of shear force and displacement with different shear speeds are almost identical as an increase of the number of reflows.

• 마이크로전자및패키징학회지
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• 제2권1호
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• pp.59-68
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• 1995

박막제조 기술 및 BGA패캐지를 이용하여 Wellcom 2000 system 소요 OCU Board 의 집적화를 구현하였다. 기존 PCB에 실장되는 소자 일부를 2 Channel BGA 패캐지로 모 듈화한 결과 약 1/6로 소형화시킬수 있었으며 8 Channel의 모율화는 현재 진행중인 다층 구조의 제조 기술 개발과 아울러 BGA 패캐지로 실현이 가능하며 1/10로집접화할수 있음을 알수 있었다. 또한 PCB위에 Bare Chip을 실장하여 Wire Bonding 한 COB를 구현하여 CBGGA의 PCB실장과 함께한 모듈을 형성해 보았다. CBGA패캐지에 Ball Shear Test, In Circuit Test 온도 환경주기시험(TCT) 진동시험을 통하여 신뢰성을 입증하였다. 이때 CBGA의 Coplanarity(3.2%) 증진을 위하여 Ceramic Pad에 선택적인 도금 방식을 개발적용 하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.109-119
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• 2003

o In order to start SIP Project .Marketing (& ASIC team) should present biz planning, schedule, device/SIP specs., in SIP TFT prior to request SIP development for package development project. .In order to prevent (PCB) revision, test, burn-in, & quality strategy should be fixed by SIP TFT (PE/Test, QA) prior to request for PKG development. .Target product price/cost, package/ test cost should be delivered and reviewed. o Minimum Information for PCB Design, Package Size, and Cost .(Required) package form factor: size, height, type (BGA, QFP), Pin count/pitch .(Estimated) each die size including scribe lane .(Estimated) pad inform. : count, pitch, configuration(in-line/staggered), (open) size .(Estimated) each device (I/O & Core) power (especially for DRAM embedded SIP) .SIP Block diagram, and net-list using excel sheet format o Why is the initial evaluation important\ulcorner .The higher logic power resulted in spec. over of DRAM Tjmax. This caused business drop longrightarrow Thermal simulation of some SIP product is essential in the beginning stage of SIP business planning (or design) stage. (i.e., DRAM embedded SIP) .When SIP is developed using discrete packages, the I/O driver Capa. of each device may be so high for SIP. Since I/O driver capa. was optimized to discrete package and set board environment, this resulted in severe noise problem in SIP. longrightarrow In this case, the electrical performance of product (including PKG) should have been considered (simulated) in the beginning stage of business planning (or design).

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.