• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1062-1069
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• 2013

This paper proposes a simple current compensation method to improve the control performance of B4 inverters. Four-switch inverters so called B4 inverters employ only four switches. They have a split dc-link and one phase of three-phase motors is connected to the center-tap of split dc-link capacitors in B4 inverters. The voltage ripples in the center tap of the dc-link generate unbalanced three-phase voltages causing current ripples. To solve this problem, this paper presents a simple compensation method that adjusts switching times considering dc-link voltage ripples. The validity of the proposed method is verified by simulations and experiments carried out with a 1 HP induction machine.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.1
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• pp.110-116
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• 2013

This paper proposes a current ripple reduction method to improve the control performance of B4 type inverter that is studied for cost-effective drive systems. B4 inverters employ only four switches and they have a center-tapped connection between the split dc-link capacitors and one phase of a three-phase motor or load. In the B4 topology, unbalanced three-phase voltages will be generated due to the dc-link voltage ripple. To solve this problem, this paper presents a voltage distortion compensation method that adjusts the voltage reference with the consideration of dc-link voltage ripple. The validity of the proposed method is verified by simulation and excremental results with an induction machine.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.154-154
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• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.317-320
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• 2000

This paper proposes a voltage compensation method to improve the control performance of B4 inverter which is studied for low-cost drive systems. The B4 inverter employs only four switches and it has a center-tapped connection in the split dc-link capacitors to one phase of a three-phase motor. In the B4 topology unbalan-cd three-phase voltages will be generated by the dc link voltage ripple. To solve this problem we present a voltage compensation method which adjusts switching times considering dc link voltage ripple. The proposed method is verified by simulation results,

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.4
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• pp.195-200
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• 2005

In this paper, we proposed the electric circuit using one common arm of H-Bridge Inverters to reduce the number of switching component in multi-level inverter combined with H-Bridge Inverters and Transformers. and furthermore we suggested the new multi-level PWM inverter using PWM level to reduce THD(Total Harmonic Distortion). and we used the switching method that can be same rate of usage at each transformer. Also, we tested the proposed prototype 9-level inverter to clarify the proposed electric circuit and reasonableness of control signal for the proposed multi-level PWM inverter.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.83-90
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• 2011

In this paper, we present the design method for a low-pass type inverter, which can effectively suppress the spurious response associated with band-pass filters. The inverter has a length of ${\lambda}/4$ and employs not only a stepped-impedance configuration but also asymmetrical and bending structures in order to improve frequency selectivity and compactness. The inverter is applied as an impedance/admittance inverter to the ultra-wideband (UWB) band-pass filter. The UWB band-pass filter configuration is based on a stub band-pass filter consisting of quarter-wavelength impedance inverters and shunt short-circuited stubs ${\lambda}/4$ in length. The asymmetrical stepped-impedance low-pass type inverter improves not only the spurious responses, but also the return loss characteristics associated with a UWB band-pass filter, while a compact size is maintained. The UWB band-pass filter using the proposed inverters is fabricated and tested. The measured results show excellent attenuation characteristics at out-band frequencies, which exceed 18 dB up to 39 GHz. The insertion loss within the pass-band (from 3.1 to 10.6 GHz) is below 1.7 dB, the return loss is below 10 dB, and the group delay is below 1 ns.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.4
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• pp.271-276
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• 2021

Arc fault detector based on multilevel DWT with analysis of high-frequency noise components over 100 kHz is proposed in this study to improve the performance in detecting serial arcs and distinguishing them from inverter noise in PV systems. PV inverters generally operate at a frequency range of 20-50 kHz for switching operation and maximum power tracking control, and the effect of these frequency components on the signal for arc detection leads to negative arc detection. High-speed ADC and multilevel DWT are used in this study to analyze frequency components above 100 kHz. Such high frequency components are less influenced by inverter noise and utilized to detect as well as separate DC series arc from inverter noise. Arc detectors identify the input current of PV inverters using a Rogowski coil. The sensed signal is filtered, amplified, and used in 800kSPS ADC and DWT analysis and arc occurrence determination in DSP. An arc detection simulation facility in UL1699B was constructed and AFD tests the proposed detector were conducted to verify the performance of arc detection and performance of distinction of the negative arc. The satisfactory performance of the arc detector meets the standard of arc detection and extinguishing time of UL1699B with an arc detection time of approximately 0.11 seconds.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.547-553
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• 1999

A new multi-step voltage source inverter is proposed in this paper. The proposed scheme is composed of t the double-connected 12-step inverter with an auxiliary circuit. The auxiliary circuit includes two voltage d dividing capacitors, two switching devices and a low KV A autotransformer. The resultant system is shown to b be a 24-step inverter suitable for medium power level SVC applications in which the PWM method can not be e employed. A 36-step operation can also be 이)tained by the addition of a bidirectional switch to the ProlXlsed I inverter. The design parameters are derived from the analysis of voltages and currents by means of switching f functions. The validity of the proposed scheme is confirmed by the simulated and experimental results.