• 전자공학회논문지C
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• 제34C권12호
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• pp.1-8
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• 1997

In this paper, a new method of state code assignment for reduction of switching activities of state transition in asynchronous circuits is proposed. The algorithm is based on a on-hot code and modifies it to reduce switching activities. To estimate switching activities as a cost functions we introduce state transition probability (STP). AS a results, the proposed algorithm has an advantage of 60% over with the conventional code assignment in terms of switching and code length of state assignment.

• 대한전자공학회논문지
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• 제11권2호
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• pp.22-26
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• 1974

변이응동 비동기순서회로를 합성하기 위하여 D-형 변이응동 flirt-flop을 사용하였다. 입력조의 상이라는 새로운 개념을 도입하여 내부상태를 감소할 수 있었다. 원시상태표로부터 직접 다입력변화 회로를 합성하는 등차를 마련하였고 실례를 들어 지금까지의 방법보다 더 나은 방법임을 실증하였다.

• 전자공학회논문지A
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• 제33A권10호
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• pp.195-204
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• 1996

We suggest a transform method form asynchronous finite state machines (AFSMs) into signal transition graphs (STGs) for speed-independent circuit synthesis. Existing works synthesize nodes in the state graph increases exponentially as the number of input and output signals increases. To overcome the problem of the exponential data complexity, we transform AFSMs into STGs so that the previous synthesis algorihtm form STGs can be applied.Accoridng to the experimental results, it turns out that our synthesis method produces more efficient circuit than the previous synthesis methods.

• 전기학회논문지
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• 제57권8호
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• pp.1440-1446
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• 2008

In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.

• 전기학회논문지
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• 제58권12호
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• pp.2484-2491
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• 2009

This paper proposes robust state feedback control of asynchronous sequential machines with model uncertainty. The considered asynchronous machine is deterministic, but its state transition function is partially known before executing a control process. The main objective is to derive the existence condition for a corrective controller for which the behavior of the closed-loop system can match a prescribed model in spite of uncertain transitions. The proposed control scheme also has learning ability. The controller perceives true state transitions as it undergoes corrective actions and reflects the learned knowledge in the next step. An adaptation is made such that the controller can have the minimum number of state transitions to realize a model matching procedure. To demonstrate control construction and execution, a VHDL and FPGA implementation of the proposed control scheme is presented.

• 전자공학회논문지SC
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• 제46권4호
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• pp.39-48
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• 2009

전역 클럭 없이 동작하는 비동기 순차 머신은 동기 순차 머신에 비해서 속도나 에너지 소비 면에서 장점을 지닌다. 본 논문에서는 불확실한 상태 천이를 가지는 입력/상태 비동기 머신을 위한 견실 제어기를 제안한다. 논문에서 고려하는 비동기 머신은 모델 불확실성, 내부 고장 등으로 인해서 일부 영역의 상태 천이 함수가 불확실하다. 이번 연구에서는 이러한 비동기 머신을 표현하는 유한 상태 머신 식을 제안한 후 일반화된 도달가능성 행렬을 이용하여 머신의 폐루프 동작이 주어진 정상적인 모델의 동작과 일치하도록 하는 비동기 제어기가 존재할 조건을 규명한다. 또한 기존 연구 결과를 바탕으로 비동기 제어기의 설계 과정을 기술하고 폐루프 시스템의 안정 상태 동작을 분석한다.

• 정보처리학회논문지A
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• 제9A권1호
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• pp.61-74
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• 2002

본 논문에서는 시간 제한 조건을 가진 자유 선택 신호 전이 그래프로부터 비동기 회로를 합성하는 방법을 기술한다. 이 방법에서는 상태 그래프를 생성하지 않고 신호 전이 그래프로부터 직접 신호 전이들간의 관계를 구하여 비동기 회로를 합성한다. 본 논문의 합성 방법에서는 자유 선택 신호 전이 그래프를 선택 행위가 없는 결정성 신호 전이 그래프에 대하여 타이밍 분석을 수행하여 임의의 두 신호 전이 사이의 시간 제약 병렬 관계와 시간 제약 인과 관계를 구한다. 다음에는 이 관계들을 이용하여 각 결정성 신호 전이 그래프에 대한 합성을 수행하고 그 결과를 합병함으로써 전체 회로를 합성한다. 실험 결과에 의하면 본 논문에서 제안한 합성 방법은 상태 공간이 큰 회로에 대하여 현저하게 합성시간을 단축시킬 수 있을 뿐 만 아니라 기존의 상태 그래프 기반 합성 방법과 비교하여 거의 같은 면적의 회로를 합성한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.887-890
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• 1998

We present a method for initialization of asynchronous circuits using binary decision space representation. From state transition graph(STG) which is given as a specification a circuit, the BDD is generated to solve the state space explosion problem which is caused by concurrecy of STG. We first step, we construct the necessary informaton as a form of K-map from BDD, then find an initial state on the K-map by assignment of don't care assignment.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2000

In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.

• 제어로봇시스템학회논문지
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• 제17권11호
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• pp.1125-1131
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• 2011

This paper presents a control theoretic approach to realizing fault tolerance in asynchronous sequential circuits. The considered asynchronous circuit is assumed to work in space environment and is subject to faults caused by total ionizing dose (TID) effects. In our setting, TID effects cause permanent changes in state transition characteristics of the asynchronous circuit. Under a certain condition of reachability redundancy, it is possible to design a corrective controller so that the closed-loop system can maintain the normal behavior despite occurrences of TID faults. As a case study, the proposed control scheme is applied to an asynchronous arbiter implemented in FPGA.