• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.8
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• pp.783-789
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• 2002

In this paper, V-band MMIC coupled oscillator arrays are presented. In the proposed array, two push-pull patch antennas are synchronized by using strong electromagnetic coupling between two antennas. As a result, total size of the array is reduced and the array can be integrated in a single chip. To verify proposed array concept, two 1$\times$2 arrays are designed and fabricated using standard 0.15 um gate length pHEMT MMIC process. The circuits are mounted in an oversized waveguide and measured. The first array shows 0.5 dBm at 56.372 GHz and the second one has an output of 5.85 dBm at 60.147 GHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

• ETRI Journal
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• v.27 no.5
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• pp.563-568
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• 2005

A motion-control chip contains major functions that are necessary to control the position of each motor, such as generating velocity command profiles, reading motor positions, producing control signals, driving several types of servo amplifiers, and interfacing host processors. Existing motion-control chips can only generate velocity profiles of fixed characteristics, typically linear and s-shape smooth symmetric curves. But velocity profiles of these two characteristics are not optimal for all tasks in industrial robots and automation systems. Velocity profiles of other characteristics are preferred for some tasks. This paper proposes a motion-control chip to generate velocity profiles of desired acceleration and deceleration characteristics. The proposed motion-control chip is implemented with a field-programmable gate array by using the Very High-Speed Integrated Circuit Hardware Description Language and Handel-C. Experiments using velocity profiles of four different characteristics will be performed.

• KSBB Journal
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• v.25 no.4
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• pp.344-350
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• 2010

This paper demonstrates a microfluidic chip incorporating patterned hollow silica beads that can be effectively used for chemotaxis assay. The hollow silica bead has been exploited to develop a carrier for chemoattractant to induce cell migration. The microfluidic chip contains a patterned array of microfabricated docks which can hold only one bead per docking site. The hollow bead placed inside microfluidic chip releases chemotactic reagent (PDGF-BB) around its periphery in a controlled fashion which generates a signal for chemotatic migration of fibroblast cells. The number of cells migrated close to each bead has been assessed. On-chip cell migration assay showed a remarkable result proving the high efficiency and reliable accuracy in quantitative analysis. Therefore, the device could be extensively used in cell migration assay and other various studies related to cellular movements.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.7
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• pp.328-334
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• 2002

The DNA chips are devices associating the specific recognition properties of two DNA single strands through hybridization process with the performances of the microtechnology. In the literature, the "Gene chip" or "DNA chip" terminology is employed in a wide way and includes macroarrays and microarrays. Standard definitions are not yet clearly exposed. Generally, the difference between macro and microarray concerns the number of active areas and their size, Macroarrays correspond to devices containing some tens spots of 500$\mu$m or larger in diameter. microarrays concern devices containing thousnads spots of size less than 500$\mu$m. The key technical parameters for evaluating microarray-manufacturing technologies include microarray density and design, biochemical composition and versatility, repreducibility, throughput, quality, cost and ease of prototyping. Here we report, a new method in which minute particles are arranged in a random fashion on a chip pattern using random fluidic self-assembly (RFSA) method by hydrophobic interaction. We intend to improve the stability of the particles at the time of arrangement by establishing a wall on the chip pattern, besides distinction of an individual particle is enabled by giving a tag structure. This study demonstrates the fabrication of a chip pattern, immobilization of DNA to the particles and arrangement of the minute particle groups on the chip pattern by hydrophobic interaction.ophobic interaction.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.3-8
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• 2013

In CDMA-based systems, recently, researches on chip-level equalization have been studied in order to improve receiving performance when supporting high-rate data services. In this paper, we consider a chip-level LMMSE (linear minimum mean-squared error) receiver for D-TxAA (dual stream transmit antenna array) based single stream HSDPA MIMO systems using precoding weights. First, we will derive precoding weights for maximizing the total instantaneous received power. We will also analyze the effects of both transmit delay of precoding weights and mobile velocity on chip-level LMMSE receivers, which is verified through computer simulations in various mobile channel environments.

• Proceedings of the Microbiological Society of Korea Conference
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• 2002.10a
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• pp.22-26
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• 2002

There are a number of ways in which environmental microbiology and microbial ecology will benefit from DNA micro array technology. These include community genome arrays, SSU rDNA arrays, environmental functional gene arrays, population biology arrays, and there are clearly more different applications of microarray technology that can be applied to relevant problems in environmental microbiology. Two types of the applications, bacterial identification chip and functional gene detection chip, will be presented. For the bacterial identification chip, a new approach employing random genome fragments that eliminates the disadvantages of traditional DNA-DNA hybridization is proposed to identify and type bacteria based on genomic DNA-DNA similarity. Bacterial genomes are fragmented randomly, and representative fragments are spotted on a glass slide and then hybridized to test genomes. Resulting hybridization profiles are used in statistical procedures to identify test strains. Second, the direct binding version of microarray with a different array design and hybridization scheme is proposed to quantify target genes in environmental samples. Reference DNA was employed to normalize variations in spot size and hybridization. The approach for designing quantitative microarrays and the inferred equation from this study provide a simple and convenient way to estimate the target gene concentration from the hybridization signal ratio.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.415-416
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• 2008

The finite element model was used to simulate the temperature distribution of a arrayed vertical-cavity surface-emitting laser (VCSEL). In this work, the dimension of AlGaAs/GaAs based VCSEL array was $50{\mu}m$ active diameter and $250{\mu}m$ pitch, and AuSn solder of 80wt%Au-20wt%Sn was included to flip-chip bond. The results of the thermal simulation will be applied to predict the thermal cross-talk in high speed parallel optical interconnects.