• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1A
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• pp.47-53
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• 2003

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7${\mu}m$ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1076-1085
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• 2001

In this paper, the FMM(Fast Multipole Method) combined with GMRES(Generalized Minimal RESidual Method) matrix solver is used to extract the parasitic impedance for complicated 3-D structures in uniform dielectric materials which limit the use of MoM(Method of Moment) due to its large computation time and memory requirement. This algorithm is a fast multipole-accelerated method based on quasistatic analysis and is very efficient for computing impedance between conductors. This paper proved the accuracy and efficiency of the FMM by comparing with MoM in simple examples. Finally the parasitic impedance of FC-PGA(Flip Chip Pin Grid Array) Package pins has been extracted by this algorithm and we have considered the possibility of the EMI/EMC problem caused by the signal interference.

• Journal of Practical Engineering Education
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• v.6 no.2
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• pp.91-97
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• 2014

Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

• Journal of Sensor Science and Technology
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• v.27 no.6
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• pp.357-361
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• 2018

This paper presents an averaging current adjustment technique for reducing the pixel resistance variation in a bolometer-type uncooled infrared image sensor. Each unit pixel was composed of an active pixel, a reference pixel for the averaging current adjustment technique, and a calibration circuit. The reference pixel was integrated with a polysilicon resistor using a standard complementary metal-oxide-semiconductor (CMOS) process, and the active pixel was applied from outside of the chip. The averaging current adjustment technique was designed by using the reference pixel. The entire circuit was implemented on a chip that was composed of a reference pixel array for the averaging current adjustment technique, a calibration circuit, and readout circuits. The proposed reference pixel array for the averaging current adjustment technique, calibration circuit, and readout circuit were designed and fabricated by a $0.35-{\mu}m$ standard CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2109-2116
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• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.111-120
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• 2016

Education equipment for field programmable gate array (FPGA) design of sensor-based IOT (Internet Of Thing) system is introduced. Because sensors have different interfaces, several types of interface controller on FPGA need. Using this equipment, several types of interface controller, which can control ADC (analog-to-digital converter) for analog sensor outputs and $I^2C$ (Inter-Integrated Circuit), SPI (Serial Peripheral Interface Bus), and GPIO (General-Purpose Input/Output) for digital sensor outputs, can be designed on FPGA. Image processing hardware using image sensors and display controller for real and image-processed images or videos can be design on FPGA chip. This equipment can design a SOC (System On Chip) consisting of a hard process core on Linux OS and a FPGA block for IOT system which can communicate with wire and wireless networks. Using the education equipment, an example of hardware design using image sensor and accelerometer is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.261-267
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• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.97-100
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• 2004

The identification of the DNA structure as a double-stranded helix consting of two nucleotide chain molecules was a milestone in modern molecular biology. The DNA chip technology is based on reverse hybridization that follows the principle of complementary binding of double-stranded DNA. DNA chip can be described as the deposition of defined nucleic acid sequences, probes, on a solid substrate to form a regular array of elements that are available for hybridization to complementary nucleic acids, targets. DNA chips based on cDNA clons, oligonucleotides and genomic clons have been developed for gene expression studies, genetic variation analysis and genomic changes associated with disease including cancers and genetic diseases. DNA chips for gene expression profiling can be used for functional analysis in human eel Is and animal models, disease-related gene studies, assessment of gene therapy, assessment of genetically modified food, and research for drug discovery. DNA chips for genetic variation detection can be used for the detection of mutations or chromosomal abnormalities in cnacers, drug resistances in cancer cells or pathogenic microbes, histocompatibility analysis for transplantation, individual identification for forensic medicine, and detection and discrimination of pathogenic microbes. The DNA chip will be generalized as a useful tool in clinical diagnostics in near future. Lab-on-a chip and informatics will facilitate the development of a variety of DNA chips for diagnostic purpose.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.140-151
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• 1996

In this paper, we analyze the variations of thermal characteristics of LD (laser diode) arrays packaged by a flip-chip bonding method. When we simulate the temperature distribution in LD arrays with a BEM (boundary element method) program coded in this paper, we find that thermal crosstalks in LD arrays packaged by the flip-chip bonding method increases by 250-340% compared to that in LD arrays packaged by previous methods. In the LD array module packaged by the flip-chip bonding technique without TEC (thermo-electric cooler), the important parameter is the absolute temperature of the active layer increased due cooler), the important parameter is the absolute temperature of th eactiv elayers of LD arrays to thermal crosstalk. And we find that the temperature of the active layers of LD arrays increases up to 125$^{\circ}C$ whenall four LDs, without a carefully designed heatsink, are turned on, assuming the power consumption of 100mW from each LD. In order to reduce thermal crosstalk we propose a heatsink sturcture which can decrease the temeprature at the active layer by 40%.

• Journal of Sensor Science and Technology
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• v.15 no.2
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• pp.112-119
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• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.