• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.131-133
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• 2004

이 논문에서는 MPEG audio 알고리즘의 필터뱅크를 덧셈을 사용하여 저전력으로 구현할 수 있는 구조를 제안하였다. 제안된 구조는 CSD(Canonic Signed Digit) 형의 계수를 사용하며, 입력신호 샘플을 최대로 공유함으로서 사용되는 덧셈기의 수를 최소화하였다. 제안된 구조는 알고리즘에서 사용된 공통입력 공유, 선형위상 대칭 필터계수를 이용한 공유, 공통입력을 이용한 블록 공유, CSD 형의 계수와 공통패턴 공유를 통하여 사용되는 덧셈의 수를 최소화할 수 있음을 보였다. Verilog-HDL 코딩을 통하여 시뮬레이션을 수행한 결과, 제안된 구조는 기존의 곱셈기 구조의 구현면적과 비교하여 $59.6\%$를 감소시킬 수 있음을 보였다. 또한 제안된 구조의 전력소모도 곱셈기 구조와 비교하여 $59.6\%$를 감소시킬 수 있음을 보였다. 따라서 곱셈기가 내장된 DSP 프로세서를 사용하지 않고도, Arithmetic Unit나 마이크로프로세서를 사용하여 효과적으로 MPEG audio 필터뱅크를 구현할 수 있음을 보였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.2 no.1
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• pp.77-85
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• 2004

Regulations and guidelines for radioactive waste disposal require detailed information about the characteristics of radioactive waste drums prior to transport to the disposal sites. However, estimation of radionuclide concentrations in the drummed radioactive waste is difficult and unreliable. In order to overcome this difficulty, scaling factor (SF) method has been used to assess the activities of radionuclides, which could not be directly analyzed. A radioactive waste assay system has been operated at Korean nuclear power plant (KORI site) since 1996 and consolidated SF concept has played a dominant role in the determination of radionuclide concentrations. However, SFs are somewhat dispersive and limited in KORI site. Therefore establishment of the assay system using more improved SFs is planned and progressed. In this paper, the scope of research is briefly introduced. For the selection of more reliable activity determination method, the accuracy of predicted SF values for each activity determination method is compared. From the comparison of each activity determination method, it is recommended that SF determination method should be changed from the arithmetic mean to the geometrical mean for more reliable estimation of radionuclide activity. Arithmetic mean method and geometric mean method are compared based on the data set in KORI system. And, this change of SF determination method will prevent an inordinate over-estimation of radionuclide inventory in radwaste drum.

• Education of Primary School Mathematics
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• v.16 no.3
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• pp.251-266
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• 2013

With elementary school students who have learned the primary concepts of the four arithmetic operations as its subjects, this study has investigated in depth how schema and transformed schema are composed by recognition of the correct concepts and connection of concepts, that is to say, what schema learners form along with transformed schema with the primary concepts of the four arithmetic operations to understand the secondary concepts when power and mixed calculations are taken into contents. It has also investigated how the subjects use the schema they have formed for themselves and the transformed schema to approach problem solving, and how their composition of concepts and schema in problem solving ability achieve transformations. As a result, we can tell that the recognition of precise primary concepts and transformed schema work as important factors in the development from the primary to the secondary concepts. Here, we can also see learn that the formation of the schema created due to the connection among the primary concepts and the recognition of them and of the transformed schema play more important roles in the development toward the secondary concepts and the solution of arithmetic problems than any other factors.

• ETRI Journal
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• v.26 no.6
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.813-816
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• 2005

In last several years, the need for the right of privacy and mobile banking has increased. The RSA system is one of the most widely used public key cryptography systems, and its core arithmetic operation IS modular multiplication. P. L. Montgomery proposed a very efficient modular multiplication technique that is well suited to hardware implementation. In this paper, the montgomery modular multiplication algorithms(CIOS, SOS, FIOS) , developed by Cetin Kaya Koc, is presented and implemented using radix-16 and Altera FPGA. Also, we undertake comparisons of power dissipation using Quatrus II PowerPlay Power Analyzer.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.67-70
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• 2003

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-${\mu}m$ process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1449-1455
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• 2010

The excitation control system of an emergency diesel generator is classified as a kind of safety-related system. Compared with other control systems in a power plant, this system is required to be more reliable and have better performance. In this paper, the digital multi-redundant excitation system for a diesel generator was proposed. The signal processing system of the proposed system makes high speed signal processing and arithmetic in excitation control possible. The improved soft start algorithm and multiple PI parameters adaptation considering the diesel generator characteristics were implemented in the proposed system. The developed system was applied to a nuclear power plant successfully.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.136-138
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• 2003

This paper describes the practical application of Non-Divergent Power Flow (NDPF) solution in power system analysis. NDPF algorithm prevents the power flow solution from diverging due to the arithmetic error in Newton method, and indicates voltage collapse point. In addition to that, NDPF solution provides us with useful information for evaluating voltage profile in such cases.