• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.53-60
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• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.3
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• pp.240-248
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• 2017

This paper describes the development of a powertrain for a 20 kW experimental electric vehicle using a surface-mounted permanent magnet synchronous motor (SPMSM) and its application to a test vehicle. Two 10 kW SPMSMs are used in the powertrain, and two-level inverters are developed by using IGBTs to derive these motors. To control the SPMSM, a control board based on a TMS320F28335 DSP module, which has fast arithmetic function and floating point operator, is used. We develop a 100 V/40 A battery pack, which includes $32{\times}4$ LiFePO4 battery cells using commercial BMS. A commercial on-board charger with 220 V (AC) input and 100 V (DC) and 18 A output is used to charge the battery pack. The performance of the developed vehicle, such as acceleration availability, maximum speed, and maximum power, is estimated based on vehicle dynamics and verified through experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.23-32
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• 2006

Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Journal of the Earthquake Engineering Society of Korea
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• v.18 no.1
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• pp.29-36
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• 2014

In industrial facilities sites, the conventional method determining the earthquake magnitude (M) using earthquake ground-motion records is generally not applicable due to the poor quality of data. Therefore, a new methodology is proposed for determining the earthquake magnitude in real-time based on the amplitude measures of the ground-motion acceleration mostly from S-wave packets with the higher signal-to-ratios, given the Vs30 of the site. The amplitude measures include the bracketed cumulative parameters and peak ground acceleration (As). The cumulative parameter is either CAV (Cumulative Absolute Velocity) with 100 SPS (sampling per second) or BSPGA (Bracketed Summation of the PGAs) with 1 SPS. The arithmetic equations to determine the earthquake magnitude are derived from the CAV(BSPGA)-As-M relations. For the application to broad ranges of earthquake magnitude and distance, the multiple relations of CAV(BSPGA)-As-M are derived based on worldwide earthquake records and successfully used to determine the earthquake magnitude with a standard deviation of ${\pm}0.6M$.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.179-182
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• 2001

This paper has been studied a wavelet based still image transmission over the wireless channel. EZW(Embedded Zerotree Wavelet) is an efficient and scalable wavelet based image coding technique, which provides progressive transfer of signal resulted in multi-resolution representation. It reduces therefore the reduce cost of storage media. Although EZW has many advantages, it is very sensitive on error. Because coding are performed in subband by subband, and it uses arithmetic coding which is a kind of variable length coding. Therefore only 1∼2bit error may degrade quality of the entire image. So study of error localization and recovery are required. This paper investigates the use of reversible variable length codes(RVLC) and data partitioning. RVLC are known to have a superior error recovery property due to their two-way decoding capability and data partitioning is essential to applying RVLC. In this work, we show that appropriate data partitioning length for each SNR(Signal-to-Noise Power Ratio) and error localization in wireless channel.

• The Korean Journal of Applied Statistics
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• v.29 no.7
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• pp.1271-1281
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• 2016

Wins above replacement (WAR) is one of the most widely used statistic among sabermatrics statistics that measure the ability of a batter in baseball. WAR has a great advantage that is to represent the attack power of the player and the base running ability, defensive ability as a single value. In this study, we proposed a hitter ability index using the sabermetrics statistics that can replace WAR based on Korea Baseball Record Data of the last three years (2013-2015). First, we calculated Batter ability index through the arithmetic mean method, the weighted average method, principal component regression and selected the method that had high correlation with WAR.

• Journal of the Korea Computer Graphics Society
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• v.14 no.1
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• pp.27-33
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• 2008

Mobile systems have relatively limited resources such as low memory, slow CPU, or low power comparing to desktop systems. In this paper, we present a new 3D mesh connectivity coding algorithm especially optimized for mobile systems(i.e., mobile phones). By using adaptive octree data structure for vertex positions, a new distance-based connectivity coding is proposed. Our algorithm uses fixed point arithmetic and minimizes dynamic memory allocation, appropriate for mobile systems. We also demonstrate test data to show the utility of our mobile 3D mesh codec.