• Journal of the Korean Vacuum Society
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• v.9 no.3
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• pp.263-266
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• 2000

This paper is focused on the fabrication of reliable Al/$TiO_2-SiO_2$/Mo antifuse, which could operate at low voltage along with the improvement in on/off state properties. Mo metal as the bottom electrode had smooth surface and high melting point, and was being kept as-deposited $SiO_2$film stable. The breakdown voltage of TiO_2-SiO_2$ stacked antifuse was better than that of same-thickness (100 $\AA$) $SiO_2$antifuse because of Ti diffusion in $SiO_2$. The improving breakdown-voltage and on-resistance can be obtained as well as the influence of hillock in the bottom metal is reduced by using double insulator. Low on-resistance (65 $\Omega$) and low programming voltage (9.0 V) can be obtained in these antifuses with 250 $\AA$ double insulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.503-507
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• 2014

The on-state resistance ($R_{ON}$) instability of standard complementary metal-oxide-semiconductor (CMOS) antifuse cells has been observed for the first time by using acceleration factors: stress current and ambient temperature. If the program current is limited, the $R_{ON}$ increases as time passes during read operation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.106-109
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• 2004

A high-density 3-transistor cell one-time programmable (OTP) ROM array using standard CMOS Gate-Oxide antifuse (AF) is proposed, fabricated, and characterized with $0.18{\mu}m$ CMOS process. The proposed non-volatile high-density OTP ROM is composed of an array of 3-T OTP cells with the 3-T consisting of an nMOS AF, a high voltage (HV) blocking transistor, and a cell access transistor, all compatible with standard CMOS technology.

• Journal of Sensor Science and Technology
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• v.4 no.3
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• pp.80-88
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• 1995

This paper presents the fabrication of a metal-insulator-metal(MIM) antifuse structure consisting of insulators sandwiched between top electrode, Al, and bottom electrode, TiW and additionally studies on antifuse properties depending on the condition of insulator. The intermetallic insulators, prepared by means of sputter, comprised of silicon oxide and tantalum oxide. In such an antifuse structure, silicon oxide layer is utilized to decrease the leakage current and tantalum oxide layer, of which the dielectric strength is lower than that of silicon oxide, is also utilized to lower the breakdown voltage near 10V. Finally sufficient low leakage current, below 1nA, and low programming voltage, about 9V, could be obtained in antifuse device comprising $Al/Ta_{2}O_{5}(10nm)/SiO_{2}(10nm)/TiW$ structure and OFF resistance of 3$3.65M{\Omega}$ and ON resistance of $7.26{\Omega}$ could be also obtained. This $Ta_{2}O_{5}/SiO_{2}$ based antifuse structures will be promising for highly reliable programmable device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.9-14
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• 2009

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.117-125
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• 1996

The variation of the interfacial and the electrical properties of SiO$_{2}$TiW layers as a function of anneal temperature was extensively investigated. During the deposition of SiO$_{2}$ on TiW chemical bonds such as SiO$_{2}$, TiW, WO$_{3}$, WO$_{2}$ TiO$_{2}$ Ti$_{2}$O$_{5}$ has been created at the SiO$_{2}$/TiW interface. At the anneal temperature of 300$^{\circ}C$, WO$_{3}$ and TiO$_{2}$ bonds started to break due to the reduction phenomena of W and Ti and simultaneously the metallic W and Ti bonds started to create. Above 500$^{\circ}C$, a part of Si-O bonds was broken and consequently Ti/W silicide was formed. Form the current-voltage characteristics of Al/Sico$_{2}$(220$\AA$)/TiW antifuse structure, it was found that the breakdown voltage of antifuse device wzas decreased with increasing annealing temperature for SiO$_{2}$(220$\AA$)/TiW layer. When r, the insulating property of antifuse device of the deterioration of intermetallic SiO$_{2}$ film, caused by the influw of Ti and W.W.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.66-67
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• 1995

• Proceedings of the Korean Vacuum Society Conference
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• 1994.06a
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• pp.27-28
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• 1994

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.408-420
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• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.