• 한국산학기술학회논문지
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• 제10권7호
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• pp.1489-1496
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• 2009

비정질 인듐-갈륨-아연 산화물 박막트랜지스터를 모델링 하여서, 능동층의 구조, 두께, 평형상태의 전자밀도에 대응하는 박막트랜지스터의 특성을 연구하였다. 단일 능동층 박막트랜지스터의 경우, 능동층이 얇을 때 높은 전계효과이동도를 보였다. 문턱전압의 절대값은 능동층의 두께가 20 nm일 때 최저치를 보였으며, 문턱전압이하 기울기는 두께에 대한 의존성을 보이지 않았다. 복층구조 능동층의 경우, 하부의 능동층이 높은 평형상태 전자밀도를 가질 때보다 우수한 스위칭 특성을 보였다. 이 경우에도 능동층의 두께가 얇을 때에 높은 전계효과 이동도를 보였다. 높은 평형상태 전자밀도의 능동층의 두께를 증가시키면 문턱전압은 음의 방향으로 이동하였다. 문턱전압이하 기울기는 능동층의 구조에 대하여 특별한 의존성을 보이지 않았다. 이상과 같은 데이터는 산화물반도체 박막트랜지스터 능동층의 구조, 두께, 도핑비율을 최적화함에 효과적으로 사용될 것으로 기대된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.142-143
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• 2006

Organic thin film transistors(OTFTs) were simulated by a SPICE model adopted in the amorphous TFTs(a-Si:H TFTs). The gate voltage-dependent mobilities were assumed to fit the representative current-voltage characteristics. The optimal fitting procedures were suggested to compare the experimental data with the mathematical expressions used in the amorphous TFTs. Each SPICE parameter explains the gate dependent mobilities in OTFTs which might originate from the influence of the hopping conduction.

• Transactions on Electrical and Electronic Materials
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• 제16권2호
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• pp.99-102
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• 2015

Thin film transistors (TFTs) with amorphous 2 wt% silicon-doped zinc tin oxide (a-2SZTO) channel layer were fabricated using an RF magnetron sputtering system, and the effect of post-annealing treatment time on the structural and electrical properties of a-2SZTO systems was investigated. It is well known that Si can effectively reduce the generation of oxygen vacancies. However, it is interesting to note that prolonged annealing could have a bad effect on the roughness of a-2SZTO systems, since the roughness of a-2SZTO thin films increases in proportion to the thermal annealing treatment time. Thermal annealing can control the electrical characteristics of amorphous oxide semiconductor (AOS) TFTs. It was observed herein that prolonged annealing treatment can cause bumpy roughness, which led to increase of the contact resistance between the electrode and channel. Thus, it was confirmed that deterioration of the electrical characteristics could occur due to prolonged annealing. The longer annealing time also decreased the field effect mobility. The a-2SZTO TFTs annealed at 500℃ for 2 hours displayed the mobility of 2.17 cm²/Vs. As the electrical characteristics of a-2SZTO annealed at a fixed temperature for long periods were deteriorated, careful optimization of the annealing conditions for a-2SZTO, in terms of time, should be carried out to achieve better performance.

• Journal of Information Display
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• 제2권3호
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• pp.72-77
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• 2001

Amorphous silicon thin-film transistors (a-Si TFTs) were incorporated into Mo-tip-based triode-type field emitters and diode-type ones of carbon nanotubes for an active-matrix cathode (AMC) plate of field emission displays. Also, we developed a novel surface-treatment process for the Mo-tip fabrication, which gleatly enhanced in the stability of field emission. The field emission currents of AMC plates on glass substrate were well controlled by the gate bias of a-Si TFTs. Active-matrix field emission displays (AMFEDs) with these AMC plates were demonstrated in a vacuum chamber, showing low-voltage matrix addressing, good stability and reliability of field emission, and highly uniform light emissions from the anode plate with phosphors. The optimum design of AMFEDs including a-Si TFTs and a new light shield/focusing grid is discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.153-161
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• 2011

In this work, we report the physics-based SPICE model of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) and demonstrate the SPICE simulation of amorphous InGaZnO (a-IGZO) TFT inverter by using Verilog-A. As key physical parameter, subgap density-of-states (DOS) is extracted and used for calculating the electric potential, carrier density, and mobility along the depth direction of active thin-film. It is confirmed that the proposed DOS-based SPICE model can successfully reproduce the voltage transfer characteristic of a-IGZO inverter as well as the measured I-V characteristics of a-IGZO TFTs within the average error of 6% at $V_{DD}$=20 V.

• 한국전기전자재료학회논문지
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• 제29권2호
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• pp.69-74
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• 2016

In this study, we proposed an a-IGZO (amorphous In-Ga-Zn-O) TFT (thin-film transistor) with off-planed source/drain structure. Furthermore, two different electrode materials (ITO and Ti) were applied to the source and drain contacts for performance improvement of a-IGZO TFTs. When the ITO with a large work-function and the Ti with a small work-function are applied to drain electrode and source contact, respectively, the electrical performances of a-IGZO TFTs were improved; an increased driving current, a decreased leakage current, a high on-off current ratio, and a reduced subthreshold swing. As a result of gate bias stress test at various temperatures, the off-planed S/D a-IGZO TFTs showed a degradation mechanism due to electron trapping and both devices with ITO-drain or Ti-drain electrode revealed an equivalent instability.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.33-36
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• 2000

Active-controlled field emitter arrays (ACFEAs) are developed by monolithically integrating molybdenum field emitter arrays with amorphous silicon thin film transistors (a-Si：H TFTs) on glass substrate. Transfer and output characteristics of the fabricated ACFEAs showed that the emission currents of FEAs can be accurately controlled by the gate bias voltages of TFTs. Also, the emission currents of the ACFEAs kept stable without any fluctuations during the 30 min-operation.

• Transactions on Electrical and Electronic Materials
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• 제18권1호
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Transactions on Electrical and Electronic Materials
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• 제18권3호
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• pp.155-158
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• 2017

In this paper, ZnO Thin Film Transistors (TFTs) were fabricated by a sol-gel method using a low-temperature process, and their physical and electrical characteristics were analyzed. To lower the process temperature to $200^{\circ}C$, we used a zinc nitrate hydrate ($Zn(NO_3)_2{\cdot}xH_2O$) precursor. Thermo Gravimetric Analyzer (TGA) analysis showed that the zinc nitrate hydrate precursor solution had 1.5% residual organics, much less than the 6.5% of zinc acetate dihydrate at $200^{\circ}C$. In the sol-gel method, organic materials in the precursor disrupt formation of a high-quality film, and high-temperature annealing is needed to remove the organic residuals, which implies that, by using zinc nitrate hydrate, ZnO devices can be fabricated at a much lower temperature. Using an X-Ray Diffractometer (XRD) and an X-ray Photoelectron Spectrometer (XPS), $200^{\circ}C$ annealed ZnO film with zinc nitrate hydrate (ZnO (N)) was found to have an amorphous phase and much more oxygen vacancy ($V_o$) than Zn-O bonds. Despite no crystallinity, the ZnO (N) had conductance comparable to that of ZnO with zinc acetate dihydrate (ZnO (A)) annealed at $500^{\circ}C$ as in TFTs. These results show that sol-gel could be made a potent process for low-cost and flexible device applications by optimizing the precursors.