• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.19-25
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• 2010

In this paper, the performance of the DoS information security algorithm is evaluated to provide the multimedia traffic between the nodes using the multicasting services. The essence technology for information security to distribute the multimedia contents is presented. Under the multicasting services, a node participating new group needs a new address and the node compares the collision with the existing nodes, then DoS attack can be occurred between the nodes by a malicious node. Using the NS2 simulator, the number of DoS attacks, the average number of trials to generate new address, and the average time to create address are analyzed. From simulation results, the efficient algorithm with relevant random number design according to the DRM network is needed to provide secure multimedia contents distribution.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.21-31
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• 2010

Recently e-business such as online financial trade and online shopping using mobile computes are widely spread. Most of mobile computers use NAND flash memory-based storage devices for storing data. Flash memory storage devices use a software called flash translation layer to translate logical address from a file system to physical address of flash memory by using mapping tables. The legacy FTLs have a problem that they must maintain very large mapping tables in the RAM. In order to address this issues, in this paper, we proposed a new caching scheme of mapping tables. We showed through the trace-driven simulations that the proposed caching scheme reduces the space overhead dramatically but does not increase the time overhead. In the case of online transaction workload in e-business environment, in particular, the proposed scheme manifests better performance in reducing the space overhead.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.137-148
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• 2012

In this paper, we proposed the location-aware coordinate routing algorithm for improving the performance of routing algorithm by using ZigBee in Smart Grid environment. A distributed address allocation scheme used an existing algorithm that has wasted in address space. The x, y and z coordinate axes from divided address space of 16 bit to solve this problems. However, coordinate routing does not take account of wireless link condition. If wiress link condition is not considered, when the routing table is updated, the nodes with bad link conditions are updated in the routing table and can be chosen as the next hop. This brings out the retransmissions because of received packet's errors. Also, because of these retransmissions, additional power is consumed. In this paper, we propose the location-aware coordinate routing algorithm considering wiress link condition, where reliable data transmission is made and the consumed enegy is minimize. and we compared and connected region and transition region of ZigBee location based routing in the aspect of average number of multi hops, subordinate packet delivery ratio, delay time, and energy consumption of proposed algorithm. It turned out that there were improvements in performances of each items.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.30-37
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• 2002

A focusing grating coupler (FGC) was not fabricated by the 'Continuous Path Control'writing strategy but by an electron-beam lithography system of more general exposure mode, which matches not only the address grid with the grating period but also an integer multiple of the address grid resolution (5 nm). To more simplify the fabrication, we are able to reduce a process step without large decrease of pattern quality by excluding a conducting material or layer such as metal (Al, Cr, Au), which are deposited on top or bottom of an e-beam resist to prevent charge build-up during e-beam exposure. A grating pitch period and an aperture feature size of the FGC designed and fabricated by e-beam lithography and reactive ion etching were ranged over 384.3 nm to 448.2 nm, and 0.5 $\times$ 0.5 mm$^2$area, respectively. This fabrication method presented will reduce processing time and improve the grating quality by means of a consideration of the address grid resolution, grating direction, pitch size and shapes when exposing. Here our investigations concentrate on the design and efficient fabrication results of the FGC for coupling from slab waveguide to a spot in free space.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.77-88
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• 2009

According to the size of NAND flash memory as the storage system of mobile device becomes large, the performance of address translation and life cycle management in FTL (Flash Translation Layer) to interact with file system becomes very important. In this paper, we propose the continuity counters, which represent the number of continuous physical blocks whose logical addresses are consecutive, to reduce the number of address translation. Furthermore we propose the prefetching method which preloads frequently accessed pages into main memory to enhance I/O performance of flash memory. Besides, we use the 2-bit write prediction and asynchronous writing method to predict addresses repeatedly referenced from host and prevent from writing overhead. The experiments show that the proposed method improves the I/O performance and extends the life cycle of flash memory. As a result, proposed CFTL (Clustered Flash Translation Layer)'s performance of address translation is faster 20% than conventional FTLs. Furthermore, CFTL is reduced about 50% writing time than that of conventional FTLs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1088-1094
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• 2021

This paper proposes a partial BMA (Broadcasting Multiple Access) network structure and D-ARP (Distributed Address Resolution Protocol) method in order to support full mesh routing function in the DAMA (Demand Assigned Multiple Access)-based MF-TDMA (Multi Frequency-Time Division Multiple Access) satellite system. The partial BMA network enables legacy router devices and routing protocols to be adopted in the satellite communication system, and decreases the amount of routing protocol overhead. In addition, we introduce the D-ARP method that help a spoke satellite node acquiring the MAC (Media Access Control) address from remote satellite nodes in none BMA satellite network. The D-ARP method provides the MAC address of remote nodes to each other nodes through the broadcasting-enabled satellite channel. And we lastly evaluate and analysis the network performance of the proposed approach.

• International Journal of Computer Science & Network Security
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• v.23 no.11
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• pp.99-109
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• 2023

The darknet is frequently referred to as the hub of illicit online activity. In order to keep track of real-time applications and activities taking place on Darknet, traffic on that network must be analysed. It is without a doubt important to recognise network traffic tied to an unused Internet address in order to spot and investigate malicious online activity. Any observed network traffic is the result of mis-configuration from faked source addresses and another methods that monitor the unused space address because there are no genuine devices or hosts in an unused address block. Digital systems can now detect and identify darknet activity on their own thanks to recent advances in artificial intelligence. In this paper, offer a generalised method for deep learning-based detection and classification of darknet traffic. Furthermore, analyse a cutting-edge complicated dataset that contains a lot of information about darknet traffic. Next, examine various feature selection strategies to choose a best attribute for detecting and classifying darknet traffic. For the purpose of identifying threats using network properties acquired from darknet traffic, devised a hybrid deep learning (DL) approach that combines Recurrent Neural Network (RNN) and Bidirectional LSTM (BiLSTM). This probing technique can tell malicious traffic from legitimate traffic. The results show that the suggested strategy works better than the existing ways by producing the highest level of accuracy for categorising darknet traffic using the Black widow optimization algorithm as a feature selection approach and RNN-BiLSTM as a recognition model.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.1
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• pp.1-14
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• 2024

Time-series forecasting is extensively used in the actual world. Recent research has shown that Transformers with a self-attention mechanism at their core exhibit better performance when dealing with such problems. However, most of the existing Transformer models used for time series prediction use the traditional encoder-decoder architecture, which is complex and leads to low model processing efficiency, thus limiting the ability to mine deep time dependencies by increasing model depth. Secondly, the secondary computational complexity of the self-attention mechanism also increases computational overhead and reduces processing efficiency. To address these issues, the paper designs an efficient multi-layer attention-based time-series forecasting model. This model has the following characteristics: (i) It abandons the traditional encoder-decoder based Transformer architecture and constructs a time series prediction model based on multi-layer attention mechanism, improving the model's ability to mine deep time dependencies. (ii) A cross attention module based on cross attention mechanism was designed to enhance information exchange between historical and predictive sequences. (iii) Applying a recently proposed sparse attention mechanism to our model reduces computational overhead and improves processing efficiency. Experiments on multiple datasets have shown that our model can significantly increase the performance of current advanced Transformer methods in time series forecasting, including LogTrans, Reformer, and Informer.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.199-201
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• 2005

USB has arguably become the most successful PC peripheral interconnect ever defined. As appearing UWB, wireless USB (WUSB) emerges very popular technology. However, the distributed Medium Access Control (MAC) does not harmonize with the topology of WUSB. In this paper, we address a novel MAC protocol for conformity with WUSB. The protocol is to handle negotiation on Distributed Reservation Protocol (DRP) including the channel time slot of WUSB.