• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.9
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• pp.24-29
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• 2000

As a result of the continuing increase in the high capacity and high speed requirement, ATM will be important technology. But previous AAL type cant support service that is variable length, low speed. So AAL2 is the most recently standardized AAL type, which is aimed at providing for the bandwidth efficient transmission of low-rate, short, and variable length packets in delay-sensitive applications. In this paper, we propose the architecture and the behavior of scalable AAL2 switch that are far different from ATM switch. Also, the performance of the designed switch is analyzed by computer simulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.429-432
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• 2004

In this paper, we propose a new sorting algorithm for ATM switch with a shared buffer which has a sequencer architecture with single queue. The proposed switch performs a sorting procedure of ATM cell based on the output port number of ATM cell with hardware implementation. The proposed architecture has a single buffer physically but logically it has function of multi-queue which is designed at most to control the conflicts in output port. In the future, this architecture will take various applications for routing switch and has flexibility for the extension of system structure. therefore, this structure is expected on good structure in effective transmission.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1401-1411
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• 1999

Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.383-386
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• 2001

This paper presents a novel multicast architecture for shared multibuffer ATM switch, which is tailored for throughput enhancement in multicast environments. The address queues for multicast cells are separated from those for unicast cells to arbitrate multicast cells independently from unicast cells. Three read cycles are carried out during each cell slot and multicast cells have chances to be read from shared buffer memory(SBM) in the third read cycle provided that the shared memory is not accessed to read a unicast cell. In this architecture, maximum two cells are queued at each fabric output port per time slot and output mask choose only one cell. Extensive simulations are carried out and it shows that the proposed architecture has enhanced throughput comparing with other multicast schemes in shared multibuffer switch architecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.83-92
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• 1997

Multipath ATM switch architectures have the potential to accommodate easily the design of high-speed and large capacity ATM switches which can handle a very large amount of switching throughputs. However, the multipath architecture inevitably encounters out-of-sequence problems. We propose a multipath switch model to analyze the out-of-sequence phenomenon. And we analyze the out-of-sequence performance dependency on the architecture parameters : the number of multipath, the trunk utilization, the switch size, and the number virtual channels/trunk. Indexing terms : ATM switch, Multipath archltecture, Out-of-sequence performance, Cell sequence integrity, Analytical model.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.10
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• pp.8-16
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• 1992

Despite recent advances in electrical switch architectures, the practical switch performance is limited by both the technological and physical constraints of electrical device and wiring. Though an optical switch can have good features, optical devices are of poor quality. Therefore, we propose and study the switching architecture based on free-space optical interconnections and electrical logic devices. And an exchanging method using packets with a parallel form is introduced to solves the blocking problem of the switch that resulted from switching packets with a serial form. The free-space optical interconnections overcome the defects of electrical switch, such as, the complex connections of the wires. The proposed and demonstrated switch is nonblocking, simple and high performable. Other attractive features of the proposed switch include the guarantee of first-in first-out packet sequence. In this thesis, we also discuss the performance of proposed switch and show the experimental results of the 4$\times$4 switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3B
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• pp.209-216
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• 2003

In this paper, we propose ATM switch structure including AAL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of AAL cells which consist of AAL type 1, AAL type 2, AAL type 3/4, and AAL type 5 cells. We propose two switch fabric methods; One supports the AAL type 2 cell processing per input port, the other global AAL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.113-122
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• 2001

Several guidelines can be developed for a satellite-based ATM switch. One of the most important of these is that the switch must provide a requirement for CLRs on the order of 10-10 to meet the QoS of high- performance traffic and avoid costly retransmissions. In this paper, the proposed approach shows not only the better traffic performance but also requires the little switching elements and buffers compared with original Knockout switch and other scheduling algorithm. As a result, the complexity becomes reduced. Simulation results indicate that proposed approach shows excellent cell loss ratio compared with existing switch architecture. Also, iii performance can be approached to the cell loss ratio, which is requirement for the satellite system, as window size increases. An(1 it shows thats low complexity is induced. Therefore, the proposed approach is appropriate for satellite on-board ATM switch architecture.