• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2000.11a
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• pp.372-375
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• 2000

퍼지 시스템은 비선형 시스템을 해석하고 제어기 설계 등에 많이 이용되고 있으나 대부분의 그 구현은 PC나 웍스테이션의 프로그램에 의존하고 있다. 고속의 동작을 요구하는 시스템이나 소형 시스템에는 전용 프로세서의 사용이 필요하다. 본 논문에서는 여러 퍼지 시스템 중에서 적은 규칙수로도 효과적인 성능을 나타내고 결론부가 선형식으로 표현되어 ASIC을 이용한 하드웨어화가 용이한 형태를 가진 TSK퍼지 추론 프로세서를 FPGA로 구현한다. ASIC의 설계는 Top-down 방식을 이용하여 전체구성은 Schematic을 이용하고 기능블록은 VHDL로 기술한다. TSK퍼지 추론의 연산은 전제부와 결론부를 병렬연산함으로써 고속처리를 구현하고 이에 필요한 제어부를 설계하였다. 또한 하드웨어 구현을 위해 실수연산을 이산화된 연산으로 바꾸고 이에 따른 나누기 연산자를 구현하였다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.12
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• pp.584-589
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• 2001

This paper presents an implementation method of multi-channel synchronized phasor measurement device, which is based on the ASIC implementation of the sliding-DFT. A time-shared multiplier structure is proposed to minimize the number of gates required for the implementation. The design is verified by the timing simulation of its operation. The effect of coefficient approximation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.82-85
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• 1998

Because ATM was originally designed for the optical fiber environment with bit error rate(BER) of 10-11, it is difficult to maintain ATM cell extraction capability in wireless environment where BER ranges from 10-6 to 10-3. Therefore, it must be proposed the algorithm of ATM cell extraction in wereless environment. In this paper, the frame structure and synchronization algorithm satisfyling the above condition are explained, and the new ASIC implementation method of this algorithm is proposed. The known method using shift register needs so many gates that it is not suitable for ASIC implementation. But in the proposed method, a considerable reduction in gate count can be achieved by using random access memory.

• Journal of Sensor Science and Technology
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• v.13 no.2
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• pp.133-138
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• 2004

Today, the obstacle detection system has massive size and restrictive detection range. To solve these problems, this paper proposes the capacitance variation detector using the variated capacitance value as a result of the obstacle approaching. If obstacle approaches, the capacitance value of capacitance sensor is increased and the operating frequency of oscillator is decreased. Then this changed frequency appears to the output of the mixer that operate down conversion. The capacitance variation detector is produced by Hynix$0.35{\mu}$ CMOS process. In experiment result, the frequency of final output is 6.81 MHz at no obstacle and 31.45 MHz at approaching obstacle. In conclusion, proposed capacitance variation detector has small size, low power consumption and easiness to set up anywhere. So it is expected to substitute the obstacle detector.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.1-11
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• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1255-1262
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• 2000

This paper proposes a hardware allocation and binding algorithm for ASIC Design. The proposed algorithm works on schedules input graph and simultaneously allocates and binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. Especially, he register allocation is executes the allocation optimal using graph coloring. This paper shows the effectiveness of the algorithm by comparing experiments to determine number of functional unit and register in advance or to separate executing allocation and binding of existing system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.104-114
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• 1995

In this paper, an intermediate representation HSFG(Hanyang Sequential Flow GRaph) and a new scheduling algorithm for the control-dominated ASIC design is presented. The HSFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. The scheduling algorithm minimizes the total operating time by reducing the number of the constraints as maximal as possible, searching a few paths among all the paths produced by conditional branches. The constraints are substitute by subgraphs, and then the number of subgraphs (that is the number kof the constraints) is minimized by using the inclusion and overlap relation among subgraphs. The proposed algorithm has achieved the better results than the previous ones on the benchmark data.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.19-28
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• 1997

This paper presents the design of an SSIC chip for synchronization between main and sub pictures in the multi channel TV system (MUCTS). This chip can resolve problems in MUCTS, such as passing through and vertical jolt phenomena. In addition, this chip rpvivides compatibility for normal/doulble scan, interlace/progressive and normal (4:3)/wide (16:9) systems and has high hjorizontal and vertical resolutions (340) dots and 150 lines). In each mode there are 1 channel, 3 channel, and 4 position display functions. This MUCTS chip including three A/D coverters, a D/A converter and seven line memories was fabricated with one chip by using the $0.8\mu\textrm{m}$ CMOS technology. The application areas of this MUCTS ASIC chip include the wide TV, projection TV and te next generation TV for the DBS (direct broadcast system).

• Proceedings of the KIEE Conference
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• 2000.11b
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• pp.336-338
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• 2000

Recently many studies have been performed for variable speed control of induction motor. Direct Torque Control(DTC) is emerging technique for variable speed control of PWM inverter driven induction motor. DTC allows the direct control of stator flux and instantaneous torque through simple algorithm. In this paper ASIC design technique using VHDL is applied to DTC based speed control of induction motor. ASIC for DTC based speed control is designed through the description of coordinate transformation, speed controller stator flux and torque estimator, stator flux and torque controller, stator flux position detector. FSM(Finite State Machine) and inverter voltage switching vector. Finally the above system has been implemented on the FPGA (XC4052XL-PG411). Simulation and experiment has been performed to verify the performance of the designed ASTC.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.23-32
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• 1998

In this paper, we propose a memory compiler to genrate embedded RAMs and ROMs for ASIC chips. We design the leaf cells to be compsoed of memory blocks. The compiler is built using tile-based method to simplify routing. The compiler can genrate any memory layouts to satisfy 64 to 4096 words and 4 to 256 bits per word. The technology we used here is 0.8.mu.m single poly double metal CMOS process. The address access time and power consumption are verifie dthrough the HSPICE simulation.