• The Journal of Korean Association of Computer Education
• /
• v.16 no.3
• /
• pp.99-105
• /
• 2013

The FPGA-based emulation is an essential step in ASIC design for validation. For emulation with maximal frequency, it is crucial to understand the FPGA characteristics. This paper attempts to analyze the performance characteristics of the modern FPGAs from renowned vendors, Xilinx and Altera, with a case study utilizing various adders and MIPS CPU. Unlike the common wisdom, ripple-carry adder (RCA) does not utilize the inherent carry-chain inside FPGAs when structurally designed based on 1-bit adders. Thus, the RCA shows the inferior performance to the other types of adders in FPGAs. Our study also reveals that FPGAs from Xilinx exhibit different characteristics from the ones from Altera. That is, the prefix adder, which is optimized for speed in ASIC design, shows the poor performance on Xilinx devices, whereas it provides a comparable speed to the IP core on Altera devices. It suggests that error-prone manual change of the original design can be avoided on Altera devices if area is permitted. Experiments with MIPS CPU confirm the arguments.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.31-40
• /
• 2005

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of mobile computing applications. In this paper, we (i) motivate the post-mask-tooling performance enhancement technique combined with the MTCMOS leakage current suppression technology, and (ii) develop a practical MTCMOS ASIC design methodology which fine-tunes and integrates best-in-class techniques and commercially available tools to fix the new design issues related to the MTCMOS technology. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um Process. The fabricated PDA processor operates at 333MHz which has been improved about $23\%$ at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.836-841
• /
• 2004

This paper describes ASIC design for brightness revision control, A LED Pixel Matrix (LPM) design and LPM in natural color LED vision. A designed chip has 256 levels of gradation correspond to each Red, Green, Blue LED pixel respectively, which have received 8bit image data. In order to maintain color uniformity by reducing the original rank error of LED, we adjusted the specific character value 'a' and brightness revision value 'b' to pixel unit, module unit and LED vision respectively by brightness characteristic function with 'Y=aX+b'. In this paper, if designed custom chip and brightness revision control method are applied to manufacturing of natural color LED vision, we can obtain good quality of image. Furthermore, it may decrease the cost for manufacturing LED vision or installing the plants.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.947-953
• /
• 2019

The purpose of this paper is to explore an ASIC design for estimating sizes and concentrations of airborne micro-particles by the means of integrating, amplifying and digitizing electric charge signals generated by photo-sensors as it receives scattered photons by the presence of micro-particles, consisting of a pre-amplifier that detects and amplifies voltage or current signal from photo-sensor that generates charges (hole-electron pairs) when exposed to visible rays, infrared rays, ultraviolet rays, etc. according to the intensity of rays; a shaper for shaping the amplified signal to a semi-gaussian waveform; two discriminators and binary counters for outputting digital signals by comparing the magnitude of the shaped signal with an arbitrary reference voltages. The ASIC with the proposed architecture and functional blocks in this study was designed with a 0.18um standard CMOS technology from Global Foundries and the operation and performances of the ASIC has been verified by the silicons fabricated by using the process.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.6
• /
• pp.1046-1055
• /
• 1994

In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.

• Journal of Internet Computing and Services
• /
• v.2 no.4
• /
• pp.25-32
• /
• 2001

The CAD tools for ASIC design, which are already developed or will be developed in the future, have their own functions and different working environments in many cases. Therefore, it would be more effective in achieving the final design goal, if we have a system called CAD framework in which these CAD tools are systematically integrated. In this paper, we introduce same novel techniques for integrating systematically such the CAD tools, which are usually developed under UNIX shell environments, into the CAD framework with the standard graphics interface such as X-windows. Some meta languages and script file formats are developed for flexible specification of the system MENU hierarchy and the data dependencies among executable programs. We integrated two existing CAD tools into our CAD framework using the techniques and find out the integrated protype system is working well under the new system environments.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.4
• /
• pp.798-804
• /
• 2003

In this paper, We have designed an advanced circuits for controlling the Ink Nozzle of Printer Head We can fully increase the number of nozzle by reducing the number of Input/Output PADs using the proposed new circuit. The proposed circuit is tested with only 20 nozzles to evaluate functional test using FPGA sample chip. The new circuit architecture can be estimated. Full circuit for controlling 320 nozzles was designed and simulated from ASIC full custom methodology, then the circuit was fabricated by applying 3${\mu}{\textrm}{m}$ CMOS process design rule.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.10
• /
• pp.31-39
• /
• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.5
• /
• pp.34-41
• /
• 2011

This paper presents a 24 channel capacitive touch sensing ASIC. This ASIC consists of analog circuit part and digital circuit part. Analog circuits convert user screen touch into electrical signal and digital circuits represent this signal change as digital data. Digital circuit also has an I2C interface for operation parameter reconfiguration from host machine. This interface guarantees the stable operation of the ASIC even against wide operation condition change. This chip is implemented with 0.18 um CMOS process. Its area is about 3 $mm^2$ and power consumption is 5.3mW. A number of EDA tools from Cadence and Synopsys are used for chip design.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.5B
• /
• pp.859-870
• /
• 2000

In this paper, an efficient H/W implementation technique for guard interval in OFDM(Orthogonal Frequency Division Multiplexing) systems is proposed and applied to ASIC chip design of an OFDM-based 25 Mbps wireless ATM modem. In OFDM systems, a cyclic prefix, longer than the largest multipath delay spread, is usually inserted to maintain the orthogonality of subchannels, by making the linear convolution of the channel ok like circular convolution inherent to the discreate Fourier domain, as well as to prevent the ISI(Intersymbol Interference) within the OFDM block. However, the OFDM system using the cyclic prefix requires an additional H/W in transmitter in order to store the original samples and to append the cyclic prefix to the beginning of each block. In this paper, a new approach using a cyclic prefix, even with a significantly lower H/W complexity. Finally, the performance of the proposed approach is demonstrated by applying it to ASIC chip design of an OFDM-based 25 Mbps wireless ATM modem.