• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.805-807
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• 2005

H.264/AVC의 프레임내 예측기법은 현 매크로블록의 이웃픽셀들로부터 예측값을 추출함으로써 인트라 픽처의 압축률을 높이는데 크게 기여했다. 그러나 모든 매크로블록에 대해 총 17가지의 후보 모드를 검사해야 하기 때문에, 전체 부호화기의 복잡도를 상당히 상승시키는 요인이기도 하다. 본 논문에서는 이 문제를 해결하기 위해, 기존의 움직임 추정 전용 하드웨어로 주로 사용되는 1차원 시스톨릭 어레이 구조에 부가적인 하드웨어를 장착하여, 움직임 추정뿐만 아니라 프레임 내 예측까지 가능한 하드웨어 구조를 제안한다. 병렬적으로 끊김이 없는 수행을 위해 프레임내 예측 알고리즘을 약간 수정했으나, 이것은 화질이나 비트스트림 크기에 영향을 거의 미치지 않는다. 제안된 구조는 연산에 대한 명령어 개수로 비교할 때, ARM 기반 시스템에서 얻을 수 있는 성능의 10배에서 40배에 달하는 높은 성능을 보여준다.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.279-282
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• 2024

The Use-after-free (UAF) bug is a long-standing temporal memory safety issue. To prevent UAF attacks, two commonly used approaches are lock-and-key and pointer nullification. Recently, ARM architecture supports the Memory Tagging Extension (MTE) that implemented a lock-and-key mechanism using a 4-bit tag during memory access. Previous research proposed a virtual address tagging scheme utilizing MTE to prevent UAF attacks. In this paper, we aimed to measure a simplified version of the previously proposed virtual address tagging scheme on real machines supporting MTE by implementing a simple module and conducting experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.102-111
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• 2005

In this paper, we propose an advanced hardware architecture for the fast inter prediction engine of the video coding standard MPEG-4 AVC. We describe the algorithm and derive the hardware architecture emphasizing and real time operation of the quarter_pel based motion estimation. The fast inter prediction engine is composed of block segmentation, motion estimation, motion compensation, and the fast quarter_pel calculator. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur & Virtex2 FPGA, and also by synthesis on Samsung 0.18 um CMOS technology. The synthesis result shows that the proposed hardware can operate at 62.5MHz. In this case, it can process about 88 QCIF video frames per second. The hardware is being used as a core module when implementing a complete MPEG-4 AVC video encoder chip for real-time multimedia application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1086-1090
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• 2004

Architecture generation is the first step in the design of software systems. Most of the qualities that the final software system possesses are usually decided at the architecture development stage itself. Thus, if the final system should be usable, testable, secure, high performance, mobile and adaptable, then these qualities or non-functional requirements should be engineered into the architecture itself. In particular, adaptability is emerging as an important attribute required by almost all software systems. The machinery and tools in the remote site surveillance and connects intelligence information machinery and tools at Internet. We need the server which uses different embedded operating system to become private use. With the progress of information-oriented society, many device with advanced technologies invented by many companies. However, the current firmware technologies have many problems to meet such high level of new technologies. In this paper, we have successfully ported linux on an embedded system, which is based on intel Strong ARM SA-1110 processor, then written several network modules for internet-based network devices.

• International Journal of Naval Architecture and Ocean Engineering
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• v.12 no.1
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• pp.892-901
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• 2020

We used a numerical method to estimate the hydrodynamic maneuvering derivatives for the heave-pitch coupling motion of an underwater glider. It is very important to assess the hydrodynamic maneuvering characteristics of a specific hull form of an underwater glider in the initial design stages. Although model tests are the best way to obtain the derivatives, numerical methods such as the Reynolds-averaged Navier-Stokes (RANS) method are used to save time and cost. The RANS method is widely used to estimate the maneuvering performance of surface-piercing marine vehicles, such as tankers and container ships. However, it is rarely applied to evaluate the maneuvering performance of underwater vehicles such as gliders. This paper presents numerical studies for typical experiments such as static drift and Planar Motion Mechanism (PMM) to estimate the hydrodynamic maneuvering derivatives for a Ray-type Underwater Glider (RUG). A validation study was first performed on a manta-type Unmanned Undersea Vehicle (UUV), and the Computational Fluid Dynamics (CFD) results were compared with a model test that was conducted at the Circular Water Channel (CWC) in Korea Maritime and Ocean University. Two different RANS solvers were used (Star-CCM+ and OpenFOAM), and the results were compared. The RUG's derivatives with both static drift and dynamic PMM (pure heave and pure pitch) are presented.

• Fire Science and Engineering
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• v.27 no.6
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• pp.83-88
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• 2013

Catastrophic disasters are sprouting out recently, i.e., the radiation leaks and the hydrofluoric acid gas leaks, etc. The restoration work for these kinds of disasters is very harmful and dangerous for human beings to handle themselves, thus allowing manless robots to fly the reconnaissance planes over to the disaster stricken areas and do the necessary work instead. For this endeavor and purpose, we created and tested an intelligent robot that can inspect those areas, using Mbed (ARM processor) technology temperature sensors and gas sensors aided by CAM (Computer-Aided Manufacturing) cameras. Also, HTTP Server, PC, androids and their combined efforts allow their remote controlled operation from far away with timing control. These intelligent robots can be on duty for 24 hours, minimizing the accidents and crimes and what not, and can respond more quickly when these misfortunes actually happen. We can anticipate the economic effects as well, derived from the reduced needs for hiring human resources.

• The Journal of Internal Korean Medicine
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• v.35 no.1
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• pp.1-11
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• 2014

Objectives : To investigate the effects of Sa-am acupuncture on muscle architecture and elastic properties of the spastic elbow flexor and to evaluate the correlation between clinical findings and parameters of real-time sonoelastography (RTS) in patients with chronic post-stroke hemiparesis. Materials and Methods : Seven patients (five males, two females) with chronic post-stroke hemiparesis were included. Sa-am acupuncture of Ganseunggyeok (肝勝格: LU8 LR4 補, HT8 LR2 瀉) was applied to the unaffected side 3 times a week for 4 weeks. During each acupuncture treatment period, patients were requested to exercise their affected arm, and spasticity and functional recovery outcomes of the affected arm were evaluated before and after Sa-am acupuncture treatment. Clinical outcomes were assessed using motricity index (MI), modified Ashworth scale (MAS), Fugl-Meyer assessment scale (FMA) and modified Barthel index (MBI) for elbow flexor spasticity. RTS images indicate the relative hardness of the examined muscles ranged from red (hard) to purple (soft) for color-scale, and from black (hard) to white (soft) for hue scale. Color and hue histograms of the biceps brachii and brachialis were analyzed using Image J software, and median red, blue, and hue pixel intensity were obtained. Results : MI and FMA score significantly increased and MAS score significantly decreased (p<0.05). F-wave maximal amplitude of affected abductor pollicis brevis significantly decreased (p<0.05). Muscle thickness of affected brachialis significantly increased (p<0.05). Red and green pixel intensity of affected brachialis significantly decreased (p<0.05). Conclusions : Our study revealed that Sa-am acupuncture is effective as a useful and safe treatment for spasticity in chronic post-stroke hemiparesis.

• The Journal of the Korea Contents Association
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• v.7 no.6
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• pp.69-78
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• 2007

In recent years, embedded mobile systems have been expanding their application domains from embedded portable devices which only execute a specialized application such as MP3 player or digital camcoder to digital convergence devices which execute more complicated applications converged various functionalities such as video and audio play, digital dictionary, DMB, games, phone, etc. As it requires the increasing hardware performance such as more faster CPU and more larger RAM, display, disk size, it has brought about a corresponding increase in power consumption. However, coupled with relatively small gains in battery capacity over recent years, the importance of software architecture including intelligent power management has become paramount. In this paper, we have ported UbiFOSTM with energy saving techniques on the ARM9-based MBA2440 platform. For energy savings, we adapted the dynamic power management and the device power management schemes based on monitoring workload. Experimental results with some well-known applications show that proposed low power technique could save energy up to 24 %.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.447-457
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• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4B
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• pp.360-367
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• 2009

In this paper, we propose a design methodology of IEEE 802.11n MAC which aims to achieve the higher throughput of more than 100Mbps in downlink as measured at the MAC-SAP and present the implementation results of MAC using the proposed design methodology. With our proposed methodology, different from the conventional design flow which has the separate codes for the protocol validation, for the network simulation, and for the system implementation, the unified code can be used for the network simulation and the implementation of software and hardware. Our MAC architecture is partitioned into two parts, Upper-layer MAC and Lower-layer MAC, in order to achieve the high efficiency for the new features of IEEE 802.11n standard. They are implemented in software and hardware respectively. The implemented MAC is tested on ARM based FPGA board.