• Title/Summary/Keyword: ADSRC

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모바일 오피스 서비스 지원을 위한 ADSRC 패킷 통신 시스템

  • Lee, Hyun;An, Dong-Hyun;Shin, Chang-Sub;Im, Chun-Sik;Park, Se-Ho;Cho, Kyung-Rok
    • Information and Communications Magazine
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    • v.19 no.9
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    • pp.77-85
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    • 2002
  • In this paper, we introduce an ADSRC(hdvanced DSRC) OFDM packet communication system which has been developed by ETRI. The ADSRC system is targeted to provide high terminal mobility, high data rate and seamless service in roadside environment for mobile office services. We discuss the requirements of the ADSRC communication system for mobile office services, and the system design specification to meet them with regard to air interface. The ADSRC packet communication systems consist of the MAC processor block, the OFDM packet modem block and the RF block. The MAC processor block handles medium access control and the test. The OFDM packet modem transmits data packets at up to 24Mbps adaptively and recovers the data from RF block. We describe the ADSRC packet communication system architecture and the ADSRC system protocol.

Development of Advanced DSRC Packet Communication Technology (차세대 DSRC 패킷 통신 기술 개발)

  • Lee Hyun;Park In-Seong;Shin Chang-Sub;Oh Hyun-Seo;Yim Choon-Sik;Cho Kyoung-Rok
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.2 no.1 s.2
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    • pp.93-100
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    • 2003
  • In this farer, An ADSRC(Advanced Dedicated Short Range Communication) packet communication system developed by ETRI is introduced. The ADSRC system has been developed to provide high-speed, short-range wireless racket communication in roadside environment for mobile office services. The requirements of the ADSRC system for mobile office services and the system design specification to meet them with regard to mobile of nce environment are discussed. The ADSRC packet communication systems consist of the MAC(Medium Access Control) Processor block the OFDM() modem block and the RF block. The MAC processor block handles medium access control. The OFDM modem transmits data packets at up to 24Mbps adaptively and recovers the data from RF block. The ADSRC packet communication system architecture is described.

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Hardware Design for Timing Synchronization of OFDM-Based WAVE Systems (OFDM 기반 WAVE 시스템의 시간동기 하드웨어 설계)

  • Huynh, Tronganh;Kim, Jin-Sang;Cho, Won-Kyung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.4A
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    • pp.473-478
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    • 2008
  • WAVE is a short-to-medium range communication standard that supports both public safety and private operations in roadside-to-vehicle and vehicle-to-vehicle communication environments. The core technology of physical layer in WAVE is orthogonal frequency division multiplexing (OFDM), which is sensitive to timing synchronization error. Besides, minimizing the latency in communication link is an essential characteristic of WAVE system. In this paper, a robust, low-complexity and small-latency timing synchronization algorithm suitable for WAVE system and its efficient hardware architecture are proposed. The comparison between proposed algorithm and other algorithms in terms of computational complexity and latency has shown the advantage of the proposed algorithm. The proposed architecture does not require RAM (Random Access Memory) which can affect the pipe lining ability and high speed operation of the hardware implementation. Synchronization error rate (SER) evaluation using both Matlab and FPGA implementation shows that the proposed algorithm exhibits a good performance over the existing algorithms.