• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.173-176
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• 2004

In this study we investigated post ELA(Excimer Laser Annealing) effect on SMC (Silicide Mediated Crystalization) poly-Si (Polycrystalline Silicon) to improve the characteristics of poly-Si. Combining SMC and XeCl ELA were used to crystallize the a-Si (amorphous Silicon) at various ELA energy density for LTPS (Low Temperature Polycrystalline Silicon). We fabricated the conventional SMC poly-Si with no SPC (Solid Phase Crystallization) phase using UV heating method[1] and irradiated excimer laser on SMC poly-Si, so called SMC-ELA poly-Si. After using post ELA we can get better surface morphology than conventional ELA poly-Si and enhance characteristics of SMC poly-Si. We also observed the threshold energy density regime in SMC-ELA poly-Si like conventional ELA poly-Si.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.153-156
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• 2004

A newly developed flexible active-matrix (AM-) electrophoretic display (EPD) is reported. The AM-EPD features: (1) low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology, (2) fully integrated scan- and data-drivers, (3) flexibility and light-weight realized by transferring the whole circuits onto a plastic substrate using $SUFTLA^{TM}$ (Surface Free Technology by Laser Annealing/Ablation) process. A large storage capacitor is formed in each pixel so that driving electric field can be kept sufficiently strong during a writing period Two-phase driving scheme, a reset-phase which erases a previous image and a writing-phase for writing a new image, was chosen to cope with EPD's high driving voltage. The flexible AM-EPD has been successfully operated with a driving voltage of 8.5 V.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.258-261
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• 2009

In this work we present a process to fabricate lowtemperature polysilicon (LTPS) TFTs on polyimide (PI) layers, spin-coated on Si-wafer used as rigid carrier. This process has been then used to fabricate elementary circuits as well as circuits for sensor applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.59-59
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• 2009

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.43.1-43.1
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• 2011

Hydrogenated amorphous Si (a-Si:H), low temperature poly Si (LTPS) 등 기존 thin film transistors (TFTs)에 사용되던 채널 물질을 대체할 재료로써 다양한 연구가 진행되고 있는 amorphous indium-gallium-zinc-oxide (a-IGZO)는 TFT에 적용하였을 때 뛰어난 전기적 특성과 재연성을 나타낼 뿐만 아니라 넓은 밴드갭을 가져 투명소자로도 응용이 가능하다. 본 연구에서는 a-IGZO의 열처리에 따른 소자의 전기적 특성과 조성 분포의 관계를 확인하기 위해 다음과 같이 실험을 진행하였다. Si/SiO2 기판 위에 DC sputter를 이용하여 IGZO를 증착하고 $350^{\circ}C$에서 열처리를 한 후 evaporator로 Al 전극을 형성시켰다. 이 때 전기적 특성의 변화를 비교하기 위해 열처리 한 샘플과 열처리 하지 않은 샘플에 대해 I-V 특성을 측정하였고, 채널 내부의 조성 분포 변화를 transmission electron microscopy (TEM)의 energy dispersive spectrometer (EDS)를 이용하여 관찰하였다. 그 결과 열처리 된 a-IGZO 채널 층의 산소 비율이 감소하였으며 전체적인 조성이 고르게 분포 되었고 전기적 특성은 향상되었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.768-771
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• 2006

Uniformity and performance characteristics of LTPS TFTs are important parameters for making advanced active-matrix displays. In this paper, we describe an SLS-based crystallization approach for producing orientation-controlled Si films with reduced concentrations of planar defects that stand to potentially deliver unprecedented levels of device uniformity and performance. Specifically, a 2-step process referred to as hybrid SLS has been developed that produces a variety of high-quality {100} surface-oriented Si films.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Journal of Information Display
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• v.5 no.1
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• pp.1-6
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• 2004

Ion shower doping with a main ion source of $P_2H_x$ using a source gas mixture of $PH_3/H_2$ was conducted on excimer-laser- annealed (ELA) poly-Si. The crystallinity of the as-implanted samples was measured using a UV-transmittance. The measured value of as-implanted damage was found to correlate well with the one calculated through/obtained from TRIM-code simulation. The sheet resistance was found to decrease as the acceleration voltage increased from 1 kV to 15 kV at a doping time of 1 min. However, it increases as the acceleration voltage increases under severe doping conditions. Uncured damage after furnace annealing is responsible for the rise in sheet resistance.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.