• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.10a
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• pp.336-339
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• 2003

A digital data logging system has been developed for the purpose of a compact offline Ocean Bottom Seismometer(OBS). The Digital Data Logger(DDL) consists of A/D system, Micom with storage memory and firmware managing data files. The A/D system acquires data of 16bit/4ch with sampling rate of 250Hz per channel. The Micom, a micro controller board with T33521 processor of 8051 class, was equipped with 8 flash memories of 128MB for data storage capacity of 1GB. The firmware stores the acquiring data in form of binary files. The DDL was designated to be compact and light and to consume low energy as possible. The DDL is to interface with PC through USB(Universal Serial Bus). The performance of the DDL has been validated through tests with respect to a 3-axis seismometer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.198-206
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• 2006

The GFSK Transceiver of 400 MHz ISM band for data communication is designed and fabricated. To reduce the occupied bandwidth of transmitted signal, the GFSK modulation is selected. The measured results of fabricated transceiver show the data rate of 2,400 bps at 8.5 kHz bandwidth, frequency deviation of less than ${\pm}3\;kHz$, sensitivity of -107 dBm at SINAD of 20 dB, BER of less than $1.8{\times}10^{-3}$ at -110 dBm input power. The fabricated transceiver is satisfied with the regulation of radio wave and has the good performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.927-930
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• 2007

As RFID systems are applied to various fields and applications such as supply chain management, asset management, location based applications etc. the requirements becomes diverse. For example, Much higher performance, TCP/IP protocol stack are required in some applications. However, low end processors based systems such as 8051 processor can not meet such requirements due to their low processing capacity and limited size of memory. In this paper a UHF band RFID system which meets the ISO 18000-6 TYPE C specification with ARM920T-based processor is implemented and tested.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.10
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• pp.903-910
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• 2000

In this paper, we describe a slave chip based on the Profibus-DP protocol and a system board to verify the developed slave chip. The Profibus-DP protocol is designed using VHDL and implemented on FPGA. The system board adopting the developed FPGA is designed FPGA is designed in which the firmware is implemented on Intel 8051 by using C language. Among the Profibus-DP protocols, low level layers from the physical layer to the data link layer is implemented in the form of hardware that we are able to greatly reduce the CPU load in processing protocols, and then higher layers could be processed by software. These technologies result in an IP to make terminal devices in the distributed control systems. Therefore, many digital logics as well as communication logics can be implemented onto SOC(System On a Chip) and it could be applied to various fieldbus-related areas.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.2
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• pp.81-88
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• 2014

In this paper, an implementation of concurrent backoff delay process on a single chip with IEEE 802.15.4 hardware and 8051 processor core that can be used for analyzing the interference on IEEE 802.15.4 channels due to WiFi traffics is studied. The backoff delay process of IEEE 802.15.4 CSMA-CA algorithm is explained. The characteristics of random number generator, timer, and CCA register included in the single chip are described with their control procedure in order to implement the process. A concurrent backoff delay process to evaluate multiple IEEE 802.15.4 channels is proposed, and a method to service the associated tasks at sequentially ordered backoff delay events occurring on the channels is explained. For the implementation of the concurrent backoff delay process on a single chip IEEE 802.15.4 hardware, the elements for the single channel backoff delay process and their control procedure are used to be extended to multiple channels with little modification. The medium access delay on each channel, which is available after execution of the concurrent backoff delay process, is displayed on the LCD of an IEEE 802.15.4 channel analyzer. The experimental results show that we can easily identify the interference on IEEE 802.15.4 channels caused by WiFi traffics in comparison with the way displaying measured channel powers.

• Journal of the Korean Society of Safety
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• v.24 no.3
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• pp.13-18
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• 2009

This paper is purposed to develop DAQ H/W, S/W and DB which can be used in developing electrical fire alarm system or in analyzing electrical fire cause, by detecting and monitoring precursor signals which have high possibility leading to electrical fire on electrical distribution wires. In this paper, developed was DAQ H/W adopting the C8051FXXX CPU which can analyze the measurement signals of current and voltage in electrical distribution wires, other CPU was investigated in view of the best digital sampling rate on the basis of previous researches for electrical fire alarm system. Also, the S/W which can interface with DAQ H/W's communication protocol and can be applied for electrical fire causes analysis, are embodied by LabVIEW. The combined DAQ H/W and S/W could analyze efficiently normal as well as abnormal electrical signals such as RMS value, instantaneous value of current and voltage, frequency signals etc, on the electrical wires. Also, DB system was constructed for recording various analysis results for precursor signals including voltage and current signals. The results by simulator and experiment showed that the suggested scheme with DAQ H/W, S/W and DB in this paper has high usability.

• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.96-98
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• 2002

This paper proposes the digital pin line checker which can extremely improve the efficiency of the pine line checking using a micro processor. The line checker is designed which can check efficiently up to maximum 2048 pin. Alarm busser is designed ringing real-timely the case that the pin line is connected differently with real node number. Accordingly the comparing and identifying work visually the node number showing on the displaying board with real node number is avoided after the electronic stimulus enforce to the pin of the fixture by the test engineer. The digital line checker is designed based on the 8051. And the effectiveness and accuracy of the proposed line checking strategy is tested by simulating the several error connections for pin lines on the small scale board.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.69-72
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• 2001

In this paper, we study about a acupuncture point and a non-acupuncture point resistance characteristics for acupuncture research. For this study, we devised resistance variation measurement system. This system is consist of 4-channel skin resistance measuring parts, filters, 12bit A/D convertor, 8051 micro-controller, and personal computer The developed system insert a low current to skin and obtains voltages from standard resistor that is convected to measurement circuit in series. The obtained voltage is converted to 12bit digital signal. Therefore the converted signal is changed to skin resistance by calculation in the personal computer. As the results of experiment, the resistance of acupuncture point and non-acupuncture point are different from each other. The acupuncture point has very fast current flows than the other non- acupuncture point.

• International Journal of Computer Science & Network Security
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• v.21 no.4
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• pp.264-271
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• 2021

From an information security perspective, protecting sensitive data requires utilizing algorithms which resist theoretical attacks. However, treating an algorithm in a purely mathematical fashion or in other words abstracting away from its physical (hardware or software) implementation opens the door to various real-world security threats. In the modern age of electronics, cryptanalysis attempts to reveal secret information based on cryptosystem physical properties, rather than exploiting the theoretical weaknesses in the implemented cryptographic algorithm. The correlation power attack (CPA) is a Side-Channel Analysis attack used to reveal sensitive information based on the power leakages of a device. In this paper, we present a power Hacking technique to demonstrate how a power analysis can be exploited to reveal the secret information in AES crypto-core. In the proposed case study, we explain the main techniques that can break the security of the considered crypto-core by using CPA attack. Using two cryptographic devices, FPGA and 8051 microcontrollers, the experimental attack procedure shows that the AES hardware implementation has better resistance against power attack compared to the software one. On the other hand, we remark that the efficiency of CPA attack depends statistically on the implementation and the power model used for the power prediction.