• Title/Summary/Keyword: 8 ms 기준

Search Result 189, Processing Time 0.02 seconds

A Theoretical Study on a Weight per Delay (지발당 장약량에 대한 이론적 연구)

  • Kim, Jong-In;Kang, Choo-Won;Kim, Jea-Wong
    • Explosives and Blasting
    • /
    • v.24 no.2
    • /
    • pp.33-39
    • /
    • 2006
  • The blasting vibration prediction in Korea is mainly carried out by the scaled distance method. The delay interval of the scaled distance method is generally considered to be 8ms, where the effect of vibration between adjacent holes is not included. In this study, the origin and issues of 8ms criterion are reviewed from literatures and Langefors' 2.5T criterion is applied to evaluate the applicabilities of 8ms, 17ms and 25ms intervals in which a vibration does not affect an adjacent hole.

An 8b 220 MS/s 0.25 um CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References (온-칩 RC 필터 기반의 기준전압을 사용하는 8b 220 MS/s 0.25 um CMOS 파이프라인 A/D 변환기)

  • 이명진;배현희;배우진;조영재;이승훈;김영록
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.41 no.10
    • /
    • pp.69-75
    • /
    • 2004
  • This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filers for temperature- and power- insensitive voltage references. The proposed RC low-pass filters improve switching noise performance and reduce reference settling time at heavy R & C loads without conventional off-chip large bypass capacitors. The prototype ABC fabricated in a 0.25 um CMOS occupies the active die area of 2.25 $\textrm{mm}^2$ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

A 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for High-Quality Video Systems (고화질 영상 시스템 응용을 위한 12비트 130MS/s 108mW $1.8mm^2$ 0.18um CMOS A/D 변환기)

  • Han, Jae-Yeol;Kim, Young-Ju;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.3
    • /
    • pp.77-85
    • /
    • 2008
  • This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

Design of a Low power Analog-to-Digital Converter with 8bit 10MS/s (8비트 10MS/s 저전력 아날로그-디지털 변환기 설계)

  • 손주호;이근호;설남오;김동용
    • The Journal of the Acoustical Society of Korea
    • /
    • v.17 no.7
    • /
    • pp.74-78
    • /
    • 1998
  • 본 논문에서는 고속의 변환속도를 갖는 파이프라인드 방식과 저전력 특성을 갖는 축차 비교 방식 구조를 혼용하여 고속, 저전력 아날로그-디지털 변환기를 설계하였다. 제안 된 구조는 축차 비교 방식의 변환에서 비교기를 파이프라인드 구조로 연결하여 홀드된 주기 에 비교기의 기준 전위를 전 비교기의 출력값에 의해 변환하도록 하여 고속 동작이 가능하 도록 하였다. 제안된 구조에 의해 8비트 아날로그 디지털 변환기를 0.8㎛ CMOS공정으로 HSPICE를 이용하여 시뮬레이션한 결과, INL/DNL은 각각 ±0.5/±1이었으며, 100kHz 사인 입력 신호를 10MS/s로 샘플링 하여 DFT측정 결과 SNR은 41dB를 얻을 수 있었다. 10MS/s의 변환 속도에서 전력 소모는 4.14mW로 측정되었다.

  • PDF

Analysis of Glyphosate and Glufosinate in Animal Feeds using LC-MS/MS (LC-MS/MS를 이용한 동물 사료 내 글라이포세이트 및 글루포시네이트 분석)

  • Lee, Ji-Su;Kim, Wanseo;Yang, Heedeuk;Park, Na-Youn;Jung, Woong;Kim, Junghoan;Kho, Younglim
    • Journal of the Korean Chemical Society
    • /
    • v.63 no.5
    • /
    • pp.342-345
    • /
    • 2019
  • The standards for the contents of glyphosate and glufosinate in foods are specific and well categorized. However, the standard of content in animal feeds is relatively inadequate and the classification is insufficient. There is also constant debate about the risk of glyphosate and glufosinate to human health, but the risk to animals has not been well studied. In this study, we established an analytical method in feeds that is estimated to be the path for animals to ingest glyphosate. The solvent extraction was carried out using 25% methanol. After centrifugation, samples were purified using solid phase extraction (SPE) and quantitatively analysed using LC-MS/MS after concentrated. Assessment of validation was conducted through detection limits, accuracy, and precision tests. The detection limits for the established method were 1.8 of ${\mu}g/kg$ of glufosinate and $2.4{\mu}g/kg$ of glyphosate. Accuracy was ranged from 94.4% to 103.4% and precision was range from 1.5% to 7.2%. Glufosinate was detected in one sample ($ND{\sim}8.8{\mu}g/kg$) and glyphosate was detected in all but one sample ($ND{\sim}337.0{\mu}g/kg$) by applying the analytical method to animal feeds (n=13).

A Study on the Characteristics of Blasting Vibration by Superposition Modeling (중첩 모델링을 통한 발파진동의 특성에 관한 연구)

  • Kang, Choo-Won;Kim, Seung-Hyun;Park, Hyun-Sik
    • Tunnel and Underground Space
    • /
    • v.16 no.4 s.63
    • /
    • pp.326-333
    • /
    • 2006
  • In this study, the vibration waveform of the single hole which is not interfered from the different blasting holes is separated, the each dominant frequency which is determinated through the Fast Fourier Transform(FFT) is measured. Also the separation waveform executed a superposition modeling which changes to delay time from 1ms to 80 ms in 1ms interval and controls the number of blasting holes from 2 holes to 15 holes in order to investigate the effect of PPV according to the duration time of the vibration and the number of blasting holes. As a result of analysis, the longer the duration time of the vibration, the longer the delay time which is not interfered from the different blasting holes and the effect regarding the number of blasting holes from inside identical delay time did not appear a lot.

Low-power Analog-to-Digital Converter for video signal processing (비디오 신호처리용 저전력 아날로그 디지털 변환기)

  • 조성익;손주호;김동용
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.24 no.8A
    • /
    • pp.1259-1264
    • /
    • 1999
  • In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.

  • PDF

A 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting applications (DMB 응용을 위한 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D 변환기)

  • Cho, Young-Jae;Kim, Yong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.11 s.353
    • /
    • pp.37-47
    • /
    • 2006
  • This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

Root Initiation in Cut Italian ryegrass Stems by Treatment of IBA (IBA 처리에 의한 이탈리안 라이그라스 줄기 절단면에서뿌리 분화 유도)

  • 김기용;최기준;성병렬;임용우;박근제;장요순;조진기
    • Journal of The Korean Society of Grassland and Forage Science
    • /
    • v.21 no.1
    • /
    • pp.31-34
    • /
    • 2001
  • When root initiation ratio of cut Italian ryegrass (Lolium multiflorum Lam.) stems was examined in several medium conditions containing different IBA concentration, most higher root initiation ratio was confirmed at 1.0 mg/$\ell$ of IBA and the ratio was 37.5%. When cut Italian ryegrass stems were treated in cold chamber at 4$^{\circ}C$ for 40 days and incubated in growth chamber at 26$^{\circ}C$ for 1 month, the root iniation result was 0.0% at MS-0 medium, 8.3% at MS-0.5IBA medium, 37.5% at MS-1.0IBA medium, 16.7% at MS-1.5IBA medium and 12.5% at MS-2.0IBA medium.

  • PDF

Monitoring of Ergosterol Biosynthesis Inhibitor (EBI) Pesticide Residues in Commercial Agricultural Products and Risk Assessment (국내 유통 농산물 중 EBI계 농약 모니터링과 위해도 평가)

  • Lee, Hee-Jung;Choe, Won-Jo;Lee, Ju-Young;Cho, Dae-Hyun;Kang, Chan-Soon;Kim, Woo-Seong
    • Journal of the Korean Society of Food Science and Nutrition
    • /
    • v.38 no.12
    • /
    • pp.1779-1784
    • /
    • 2009
  • Establishment of simultaneous analysis method and monitoring for individually analyzing residual eight ergosterol biosynthesis inhibitors, EBI (difenoconazole, diniconazole, fenarimol, fenbuconazole, hexaconazole, myclobutanil, nuarimol and paclobutrazol) pesticides in commercial agricultural products, were conducted. The simultaneous analysis method for the pesticides was established using a GC/MS/MS for EBI pesticides. Residual amount of those pesticides were investigated in 989 commercial agricultural products (fifteen kinds of cereal grains, vegetables, beans, nuts, fruits and mushrooms) from seven metropolitan cities and eight provinces. In EBI pesticides analysis, linearity of GC/MS/MS analysis was 0.9974-0.9992, and that of recoveries were 86-135% with relative standard deviations (RSD) <20%. The limit of quantification (LOQ) of the method ranged from 0.5 to 5.0 mg/kg for eight EBI pesticides. According to the monitoring of the EBI pesticides in commercial agricultural products, difenoconazole, fenarimol, hexaconazole showed various residual levels (total frequency of 8/989 detection, 0.8%). Paclobutrazole showed in excess levels of the MRLs (maximum residue limits) for pesticides in one chard sample by the Korea Food Code. As a result of exposure assessment on the detected 8 individual pesticides, all pesticides (difenoconazole, fenarimol, hexaconazole, paclobutrazole) were evaluated as safe level in comparison to toxicologically acceptable daily intake.