• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.97-100
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• 1999

Mobile network applications are growing and this requires a fast and efficient transport method between the BS(Base Station) and the MSC(Mobile Switching Center). One possible solution is to use ATM and a voice CODEC standard which compresses 64kbps voice data to less than 8kbps. The low bit tate and small-sized packets made by the voice CODEC imply that significant amount of link bandwidth would be wasted, if this small-sized packet is carried by one ATM cell. The cell assembly delay increases if one ATM cell is fully filled with the small-sized packets. For the bandwidth-efficient transmission of low-rate, short, and variable length packets in delay sensitive applications, AAL-2 was standardized. This paper evaluates performance of AAL-2 by using voice CODEC standard.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.113-116
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• 1999

This paper presents a hardware architecture of AAL(ATM Adaptation Layer) type 2 switch. The proposed architecture can assign and configure maximum AAL2 CID limit. AAL2 is the protocol which has been recommended by ITU-T and ATM-Forum for low bit rate delay sensitive services. The architecture assumes 155 Mbps STM-1/STS-3c physical interface, maximum VCC can be 64K connections. It can support maximum 16,384M AAL2 connections. For efficient use of peripheral memory, a concept of segment address was proposed. The proposed AAL2 switch hardware architecture can be used in ATM network as a standalone server or embedded module in a ATM switching system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.130-139
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• 1994

Video compression algorithms are based on removing spatial and/or temproal redundancy inherent in image sequences by predictive(DPCM) encoding, transform encoding, or a combination of predictive and transform encoding. In this paper, each 8$\times$8 DCT coefficient of DFD(displaced frame difference) is adaptively quantized by one of the four quantizers depending on total distortion level, which is determined by characteristics of HVS(human visual system) and buffer status. Therefore, the number of possible quantizer selection vectors(patterns) is 4$^{64}$. If this vectors are coded, toomany bits are required. Thus, the quantizer selection vectors are limited to 2048 for Y and 512 for each U, V by the proposed method using SWAD(sum of weighted absolute difference) for discriminating vectors. The computer simulation results, using the codebook vectors which are made by the proposed method, show that the subjective and objective image quality (PSNR) are goor with the limited bit allocation. (17Mbps)

• The Journal of Engineering Research
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• v.3 no.1
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• pp.57-64
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• 1998

This paper presents an architecture of a real-time two-dimensional median filter. The architecture has appropriate characteristics for the VLSI implementation such as small memory requirements, regular computations, and local data transfers. For the efficient two-dimensional median filter, a separable two-dimensional median filtering structure and a bit-sliced pipelined median searching algorithm are used. A behavioral simulator is implemented with C language and used for the analysis of the presented architecture.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.64-71
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• 1994

In this study, optimizing BPOFs are encoded by Simulated Annealing algorithm that is widely used among the optimization algorithms. Two BPOFs are trained by digit patterns, 0~9, and the digits each having 4 intraclass patterns are multiplexed. When each digit is encoded by four bit binary code, from the results of computer simulation, the correlation pezk is shown at binary value 1 position among the spatially separated four positions at the correlation plane And then, the designed BPOFs are implemented by CGH technique. Through the optical correlation experiment, satisactory results are achieved, inspite of some experimental errors and information loss owing to the amplitude type CGH filter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.2
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• pp.64-69
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• 2003

In this paper, I introduce a simple design method using existing filter design method, such as Parks-McClecllan algorithm, for root-squared type raised cosine filter with equiripple characteristics, Thought some design examples, we show that the proposed filter has much better performance in ripple than the conventional SRCF at the expense of small increasing of ISI. In addition, the proposed filter is compatible with conventional SRCF. Finally, the filter for W-CDMA which uses RRC (Root Raised Cosine) with a=0.22 is designed in 12bit finite precision.

• The Journal of the Acoustical Society of Korea
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• v.15 no.3E
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• pp.13-18
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• 1996

A real-time identifier for the nonstationary time-varying signals and systems was implemented using a low cost DSP (digital signal processing) chip. The identifier is comprised of I/O units, a central processing unit, a control unit and its supporting software. In order t estimate the system accurately and to reduce quantization error during arithmetic operation, the firmware was programmed with 64-bit extended precision arithmetic. The performance of the identifier was verified by comparing with the simulation results. The implemented real-time identifier has negligible quantization errors and its real-time processing capability crresponds to 0.6kHz for the nonstationary AR (autoregressive) model with n=4 and m=1.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.407-410
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• 2003

현재 통신시스템에서 많이 사용되고 있는 Xilinx FPGA를 이용하여, 여러 가지 로직을 구현하고 데이터 전달특성을 분석하기 위하여 신호의 노이즈와 데이터 손실을 방지하기 위하여 10층의 PCB(Printed Circuit Board)를 만들었다. FPGA에 클럭과 64bit의 데이터를 동기 시켜 전송선로의 길이의 변화와 입력된 클럭의 주파수 변화에 따른 최대 안정된 데이터 전달속도와 전송선로의 길이를 알아보았다. 제작된 PCB보드에서 FPGA의 출력 핀에서 출력포트 사이의 전송선로 길이는 13cm이며 확장된 테스트용 전송선로 보드의 길이는 30cm, 60cm, 120cm이다. 그러므로 전송선로의 길이를 13cm, 43cm, 73cm, 133cm간격으로 측정하였으며, 데이터 전송특성에 대한 클럭 주파수는 10MHz, 50MHz, 100MHz, 125MHz, 150MHz로 나누어 측정하였다. 데이터 전달 특성에서 125Mbps까지는 불가능 하지만 전송선로의 길이가 30cm일 경우 최대 100Mbps까지 안정하게 데이터를 전달할 수 있었다.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04b
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• pp.193-195
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• 2001

최근 인터넷 및 이동 통신이 발달하면서 많은 사용자들 동시에 서비스할 수 있는 고성능 데이터베이스 서버가 필요하게 되었다. 또한 DRAM의 가격이 하락하고 64bit 어드레싱이 일반화되어 쉽게 수십 GB의 메모리의 서버 플랫폼을 갖추게 되어 메인 메모리 DBMS에 대한 관심이 높아지고 있다. 본 논문에서는 2세대 고성능 메인 메모리 DBMS인 P*TIME을 소개한다. P*TIME은 CPU에 비해 상대적으로 느린 메모리 성능, 저가의 멀티 프로세서 시스템 등의 현재 하드웨어 아키텍쳐를 고려한 인덱스 및 동시성 제어 기법을 활용하였고 하였고, differential logging을 사용하여 logging과 회복을 각각 병렬적으로 수행할 수 있다. 이로 인해 검색과 갱신에서 매우 높은 성능을 나타낸다. 또한 간단한 구조로 인하여 시스템 튜닝과 커스터마이징이 용이하며, 다양한 응용 프로그램 서버 구조를 수용할 수 있다. 디렉토리 서버로서 P*TIME의 성능을 실험한 결과 SUN Enterprise 6500 서버에서 내장 디렉토리 서버 환경으로 60~70만 TPS의 검색 성능을 보이며 10만 TPS 이상의 생신 성능을 보인다. 또한 클라이언트/서버 환경에서도 10만 TPS 이상의 검색 성능을 나타내었다.

• Journal of Computing Science and Engineering
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• v.11 no.1
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• pp.1-8
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• 2017

Naive Bayes nearest neighbor (NBNN) is a simple image classifier based on identifying nearest neighbors. NBNN uses original image descriptors (e.g., SIFTs) without vector quantization for preserving the discriminative power of descriptors and has a powerful generalization characteristic. However, it has a distinct disadvantage. Its memory requirement can be prohibitively high while processing a large amount of data. To deal with this problem, we apply a spherical hashing binary code embedding technique, to compactly encode data without significantly losing classification accuracy. We also propose using an inverted index to identify nearest neighbors among binarized image descriptors. To demonstrate the benefits of our method, we apply our method to two existing NBNN techniques with an image dataset. By using 64 bit length, we are able to reduce memory 16 times with higher runtime performance and no significant loss of classification accuracy. This result is achieved by our compact encoding scheme for image descriptors without losing much information from original image descriptors.