• Title/Summary/Keyword: 3D-stacked

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Stacked Pad Area Away Package Modules for a Radio Frequency Transceiver Circuit (RF 송수신 회로의 적층형 PAA 패키지 모듈)

  • Jee, Yong;Nam, Sang-Woo;Hong, Seok-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.10
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    • pp.687-698
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    • 2001
  • This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

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3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

A Novel Air-Gap Stacked Microstrip 3 dB Coupler for MMIC (공기 절연 적층형 마이크로스트립 구조의 새로운 3 dB 커플러 MMIC)

  • 류기현;김대현;이재학;서광석
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.10 no.5
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    • pp.688-693
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    • 1999
  • This paper presents a very simple coupled line structure for MMIC which uses stacked microstrip line and does not employ any dielectric process step. For the analysis and optimization of these coupled line structure, HP-Momentum was used. The measured performance of 3 dB coupler shows 23 to 45 GHz broadband characteristics. Additionally, a balanced 2-stage Ka-Band power amplifier which uses the proposed 3 dB coupler, was also fabricated.

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Warpage and Solder Joint Strength of Stacked PCB using an Interposer (인터포저를 이용한 Stacked PCB의 휨 및 솔더 조인트 강도 연구)

  • Kipoong Kim;Yuhwan Hwangbo;Sung-Hoon Choa
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.40-50
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    • 2023
  • Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. For the s tacked PCB, it i s very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240℃ or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.

Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

  • Baek, Myung-Hyun;Kim, Do-Bin;Kim, Seunghyun;Lee, Sang-Ho;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.2
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    • pp.260-264
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    • 2017
  • Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

Fabrication of Lateral and Stacked Color Patterns through Selective Wettability for Display Applications

  • Hong, Jong-Ho;Na, Jun-Hee;Li, Hongmei;Lee, Sin-Doo
    • Journal of Information Display
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    • v.11 no.4
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    • pp.140-143
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    • 2010
  • A simple and versatile method of fabricating color patterns in two-dimension (2D) and three-dimension (3D) was developed using the selective-wettability approach. Red, green, and blue color elements are sequentially formed on a single substrate in a pattern-by-pattern and/or pattern-on-pattern fashion, through a simple coating process. Either 2D or 3D structures in an array format are produced by controlling the thickness of the hydrophobic layer (HL) coating a substrate within the framework of wetting transition. Moreover, it was demonstrated that the stacked geometry of two successive patterns can be easily tailored for various types of color arrays, with the pattern fidelity of a few tens of nanometers in terms of only a parameter of the HL thickness.

A design of silicon based vertical interconnect for 3D MEMS devices under the consideration of thermal stress (3D MEMS 소자에 적합한 열적 응력을 고려한 수직 접속 구조의 설계)

  • Jeong, Jin-Woo;Kim, Hyeon-Cheol;Chun, Kuk-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.112-117
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    • 2008
  • Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

High Isolation and Linearity MMIC SPDT Switch for Dual Band Wireless LAN Applications (이중대역 무선랜 응용을 위한 높은 격리도와 선형성을 갖는 MMIC SPDT 스위치)

  • Lee, Kang-Ho;Koo, Kyung-Heon
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.1 s.343
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    • pp.143-148
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    • 2006
  • This paper presents a high isolation and power-handling single-pole double-throw(SPDT) switch for dual band wireless LAN applications. The switch circuit has asymmetric topology which uses stacked-gate to have high power-handling and isolation for the Tx path. The proposed SPDT switch has been designed with optimum gate-width, bias, and number of stacked-gate FET. This SPDT switch has been implemented with $0.25{\mu}m$ GaAs pHEMT process which has Gmmax of 500mS/mm and fmax of 150GHz. The designed SPDT switch has the measured insertion loss of better than 0.9dB and isolation of better than 40dB for the Tx path and 25dB for the Rx path and the high power handling capability with PldB of about 23dBm for control voltage of -3/0V. The fabricated SPDT switch chip size is $1.8mm{\times}1.8mm$.

A Highly Efficient Dual-Mode 3G/4G Linear CMOS Stacked-FET Power Amplifier Using Active-Bypass

  • Kim, Unha;Kim, Yong-Gwan;Woo, Jung-Lin;Park, Sunghwan;Kwon, Youngwoo
    • Journal of electromagnetic engineering and science
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    • v.14 no.4
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    • pp.393-398
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    • 2014
  • A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power ($P_{out}$) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high- and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using a silicon-on-insulator (SOI) CMOS process operates with an idle current of 5.5 mA and shows power-added efficiency (PAE) of 20.5%/43.5% at $P_{out}$ = 12.4 / 28.2 dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39 dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and $ACLR_{E-UTRA}$ of -33 dBc at $P_{out}$ = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.

Fabrication of Micro-/Nano- Hybrid 3D Stacked Patterns (나노-마이크로 하이브리드 3차원 적층 패턴의 제조)

  • Park, Tae Wan;Jung, Hyunsung;Bang, Jiwon;Park, Woon Ik
    • Journal of the Korean institute of surface engineering
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    • v.51 no.6
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    • pp.387-392
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    • 2018
  • Nanopatterning is one of the essential nanotechnologies to fabricate electronic and energy nanodevices. Therefore, many research group members made a lot of efforts to develop simple and useful nanopatterning methods to obtain highly ordered nanostructures with functionality. In this study, in order to achieve pattern formation of three-dimensional (3D) hierarchical nanostructures, we introduce a simple and useful patterning method (nano-transfer printing (n-TP) process) consisting of various linewidths for diverse materials. Pt and $WO_3$ hybrid line structures were successfully stacked on a flexible polyimide substrate as a multi-layered hybrid 3D pattern of Pt/WO3/Pt with line-widths of $1{\mu}m$, $1{\mu}m$ and 250 nm, respectively. This simple approach suggests how to fabricate multiscale hybrid nanostructures composed of multiple materials. In addition, functional hybrid nanostructures can be expected to be applicable to various next-generation electronic devices, such as nonvolatile memories and energy harvesters.