• 대한기계학회논문집A
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• 제28권12호
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• pp.1958-1967
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• 2004

This paper describes the method to rapidly fabricate the large-sized physical model with the envelope model size of more than 600 mm${\times}$ 600 mm${\times}$ 600 mm using two type semi-automatic VLM-ST processes in connection with the reverse engineering technology. The fabrication procedure of the large-sized solid shape is as follows: (1) Generation of STL data from 3D scan data using 3D scanner, (2) generation of shell-type STL data by Boolean operation, (3) division of shell-type STL data into several pieces by solid splitting, (4) generation of USL data for each piece with VLM-Slicer, (5) fabrication of each piece by cutting and stacking according to USL data using VLM-ST apparatus, (6) completion of a shell-type prototype by zigzag stacking and assembly for each piece, (7) completion of a 3D solid shape by foam backing, (8) surface finish of a completed 3D solid shape by coating and sanding. In order to examine the applicability of the proposed method, the miniature of the Mount Rushmore Memorial has been fabricated. The envelope model size of the miniature of the Mount Rushmore Memorial is 1,453 mm${\times}$ 760 mm${\times}$ 853 mm in size. From the result of the fabricated miniature of the Mount Rushmore Memorial, it has been shown that the method to fabricate the large object using two type semi-automatic VLM-ST processes in connection with the reverse engineering technology are very fast and efficient.

• Journal of electromagnetic engineering and science
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• 제11권4호
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.1208-1211
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• 1996

In this paper, an efficient and robust robot path planning technique is discussed. Concentric Ripple Edge Evaluation and Progression( CREEP ) algorithm[1] has been elaborated and expanded to carry out 3-D path planning. Like the 2-D case, robot can always find a path, if one exists, in a densely cluttered, unknown and unstructured 3-D obstacle environment. 3-D space in which the robot is expected to navigate is modeled by stacking cubic cells. The generated path is resolution optimal once the terrain is fully explored by the robot or all the information about the terrain is given. Path planning times are significantly reduced by local path update. Accuracy and efficiency of wave propagation in CREEP algorithm are achieved by virtual concentric sphere wave propagation. Simulations in 2-D and 3-D spaces are performed and excellent results are demonstrated.

• ETRI Journal
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• 제36권4호
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Composites Research
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• 제29권6호
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• pp.342-346
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• 2016

경량화 소재 중 CFRP(Carbon Fiber Reinforced Plastic)는 카본 섬유를 이용한 섬유구조물이다. 카본과 플라스틱의 특성을 갖는 복합소재이다. 섬유구조는 섬유방향으로 큰 강도를 갖는다. 이러한 경량 소재인 CFRP로 가장 많이 사용되는 것은 직조된 CFRP이다. 직조된 CFRP는 단방향 CFRP에 비하여 구조가 안정적이기 때문이다. 단직조된 CFRP는 고가이다. 따라서 본 연구는 단방향 CFRP의 섬유 구조 특성을 파악하고자 하였다. 본 연구에서는 적층각도 [0/X/-X/0]로 X를 변수로 갖는다. X의 각도 위상이 반전되어 적층된 단방향 CFRP이다. 이러한 단방향 CFRP를 이용하여 중앙 크랙을 갖는 두께 2 mm 판재 형태의 해석 모델을 이용하였다. 해석에서는 핀으로 연결된 상부와 하부에서 하중이 가해지고 있으며 중앙 크랙부분에서 파단을 연구한다. 해석 모델은 CATIA를 이용한 3D Surface 모델로 설계하였다. CFRP 적층을 위해, ANSYS프로그램에서 ACP를 이용한 적층 방향을 결정하여 2개의 적층들을 갖는 해석 모델을 만들었다. 이후 구조해석을 진행하였다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.1259-1264
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• 2007

Microstereolithography technology has potential capability for fabrication of 3D microstructures. It evolved from conventional SLA which is one of the RP processes. In a microstereolithography process, 3D microstructures can be easily fabricated by continuously stacking 2D layer which is photopolymerized using a liquid prepolymer. Combination between biocompatible/biodegradable photocurable prepolymer and 3D complex fabrication in microstereolithography makes broad application areas such as medical, pharmaceutic, and bio devices. In particular, a 3D microneedle for transdermal drug delivery and a scaffold for tissue engineering are fabricated using this technology. In this paper, the authors address development of microstereolithography system adapted to large surface and fabrication of various microstructures. In addition, to apply human body we suggest a biodegradable 3D microneedle and a scaffold using biodegradable photocurable prepolymer.

• 한국세라믹학회지
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• 제32권7호
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• pp.761-768
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• 1995

Double layered BaTiO3 thin films with high dielectric constant as well as good insulating property were prepared for the application to low voltage driving thin film electroluminescent (TFEL) device. BaTiO3 thin films were formed by rf-magnetron sputtering technique. Amorphous and polycrystalline BaTiO3 thin films were deposited at the substrate temperatures of room temperature and 55$0^{\circ}C$, respectively. Two kinds of films prepared under these conditions showed high resistivity and high dielectric constant. The figure of merit (=$\varepsilon$r$\times$Eb.d) of polycrystalline BaTiO3 thin film was very high (8.43$\mu$C/$\textrm{cm}^2$). The polycrystalline BaTiO3 showed a substantial amount of leakage current (I), under the high electric field above 0.5 MV/cm. The double layered BaTiO3 thin film, i.e., amorphous BaTiO3 layer coated polycrystalline BaTiO3 thin film, was prepared by the new stacking method and showed very good dielectric and insulating properties. It showed a high dielectric constant fo 95 and leakage current density of 25 nA/$\textrm{cm}^2$ (0.3MV/cm) with the figure of merit of 20$\mu$C/$\textrm{cm}^2$. The leakage current density in the double layered BaTiO3 was much smaller than that in polycrystalline BaTiO3 under the high electric field. The saturated brightness of the devices using double layered BaTiO3 was about 220cd/$m^2$. Threshold voltage of TFEL devices fabricated on double layered BaTiO3 decreased by 50V compared to the EL devices fabricated on amorphous BaTiO3.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 추계학술대회 논문집
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• pp.1080-1083
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• 1997

Micro-stereolithography is a newly proposed technology as a means that can fabricate 3D micro-structures of free form. It makes a 3D structure by dividing the shape into many slices of relevant thickness along honzontal surfaces, hardening each layer of slice with a laser, and stacking them up to a des~red shape. Scale effect becomes important in this micro-fabrication process, d~fferently from the conventional stereolithography. To realize this micro-stereolithography technology, we developed an equipment using Ar+ laser, xyz stages, controllers and all the optic devices. Using the equipment, a number of micro-structures were successfully fabricated including a winecup of several tens of micrometers.

• 한국기계가공학회지
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• 제17권5호
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• pp.143-148
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• 2018

3D printing has been expanding beyond the bio/nano field to the automobile and aviation industries. 3D-printing technology has to overcome real problems to have economic value compared to its unlimited usability. Typically, the difference in mechanical strength along the lamination direction requires sufficient research to ensure reliability. In this paper, we study the anisotropic properties of ABS based on the stacking method of FDM 3D printing. Specifically, the mechanical properties of ABS material are determined through a tensile test and 3-point bending test, and the in-plane orthotropic properties are ascertained.

• 마이크로전자및패키징학회지
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• 제19권2호
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.