Journal of electromagnetic engineering and science

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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GHz EMI Characteristics of 3D Stacked Chip PDN with Through Silicon Via (TSV) Connections

  • Received : 2011.05.16
  • Published : 2011.12.31
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Abstract

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

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References

  1. Sandra Winkler, Advanced IC Packaging, 2007 Edition, Electronic Trend Publications. 2007.
  2. S. Linder, H. Baltes, F. Gnaedinger, and E. Doering, "Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers," in Proc. MEMS, pp. 349-354, 1994.
  3. L. L. W. Leung, K. J. Chen, "Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates," IEEE Transaction on Microwave Theory and Techniques, vol. 53, no. 8, pp. 2472-2480, Aug. 2005. https://doi.org/10.1109/TMTT.2005.852782
  4. U. Kang, et al., "8 Gb 3-D DDR3 DRAM using through- silicon-via technology," IEEE Journal of Solid- State Circuit, vol. 45, no. 1, Jan. 2010.
  5. C. Ryu, D. Chung, Junho Lee, K. Lee, T. Oh, and J. Kim, "High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package," IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 151-154, Oct. 2005.
  6. J. S. Pak, C. Ryu, and J. Kim, "Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation," in Proceedings of the 9th International Symposium on Electronic Materials and Packaging, Daejeon, Korea, Nov. 2007.
  7. J. S. Pak, J. Cho, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim, "Slow wave and dielectric quasi-TEM modes of metal-insulator-semiconductor structure through silicon via in signal propagation and power delivery in 3D chip package," Proc. of the 60th Electronic Components and Technology Conference 2010 (ECTC 2010), Las Vegas, USA, Jun. 2010.
  8. J. S. Pak, J. Kim, J. Cho, K. Kim, T. Song, S. Ahn, J. Lee, H. Lee, K. Park, and J. Kim, "PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip-PDN models," the IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 1, no. 2, pp. 208-219, Feb. 2011. https://doi.org/10.1109/TCPMT.2010.2101771

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