• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.157-162
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• 2005

The wafer's size has been increased up to 300mm according as the devices have been integrated sophisticatedly. For this process to make 300mm-wafer, it is required strict level which removes the particulates on the surface of wafer. Therefore we need new type wet-station which can reduce DI water and chemical in the cleaning process. Moreover, it is very important to control the temperature and the concentration of chemical wet-stat ion. The chemical supply system which is used currently is not only difficult to make a fit mixing rate of chemical in cleaning process, but also it is difficult to make fit quantity and temperature. We propose new chemical supply system, which overcomes the problems via analysis of fluid and thermal transfer on chemical supply system,

• 대한기계학회논문집B
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• 제30권4호
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• pp.306-313
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• 2006

Automated material handling system is being used as a method to reduce manufacturing cost in the semiconductor and flat panel displays (FPDs) manufacturing process. Those are considering switch-over from the traditional cassette system to single-substrate transfer system to reduce raw materials of stocks in the processing line. In the present study, the wafer transportation speed has been evaluated by numerical and experimental method for three propulsion nozzle array (face, front, rear) in an air levitation system. Test facility for 300 mm wafer was equipped with two control tracks and a transfer track of 1,500mm length. The diameter of propulsion nozzle is 0.8mm and air velocity of wafer propulsion is $50\sim150m/s$. We found that the experimental results of the wafer transportation speed were well agreed with the numerical ones. Namely, the predicted values of the maximum wafer transportation speed are higher than those values of experimental data by 16% and the numerical result of the mean wafer transportation speed is higher than the experimental result within 20%.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1996년도 The 9th KACG Technical Annual Meeting and the 3rd Korea-Japan EMGS (Electronic Materials Growth Symposium)
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• pp.88-138
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• 1996

Electronics grew up to the largest industry in the world supported by Si wafer. In near future, the Si wafer may use 300mm in diameter for economic requirement. This size wafer may use to produce large logic chip, 256Mbit DRAM, and other large complex and high density chip. Then, the quality including flatness and crustal characters may be required very high performance. And, their price should be reasonable and high quantity may be required. These requirements should be solve lot of hard problems of crystal growth, wafering mechanical processing and their cost problems. In this presentation, I may discuss following items.

• Journal of Mechanical Science and Technology
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• 제20권9호
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• pp.1492-1501
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• 2006

A transportation system of single wafer has been developed to be applied to semiconductor manufacturing process of the next generation. In this study, the experimental apparatus consists of two kinds of track, one is for propelling a wafer, so called control track, the other is for generating an air film to transfer a wafer, so called transfer track. The wafer transportation speed has been evaluated by the numerical and the experimental methods for three types of nozzle position a..ay (i.e., the front-, face- and rear-array) in an air levitation system. Test facility for 300mm wafer has been equipped with two control tracks and one transfer track of 1500mm length from the starting point to the stopping point. From the present results, it is found that the experimental values of the wafer transportation speed are well in agreement with the computed ones. Namely, the computed values of the maximum wafer transportation speed $V_{max}$ are slightly higher than the experimental ones by about $15{\times}20%$. The disparities in $V_{max}$ between the numerical and the experimental results become smaller as the air velocity increases. Also, at the same air flow rate, the order of wafer transportation speeds is : $V_{max}$ for the front-array > $V_{max}$ for the face-array > $V_{max}$ for the rear-array. However, the face-array is rather more stable than any other type of nozzle array to ensure safe transportation of a wafer.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.747-748
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• 2007

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2553-2556
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• 2003

In the semiconductor equipment industry, the SECS/GEM protocol has been recognized as the communication standard, but in our 300mm wafer aligner being developed, this capability has not been equipped yet. In this study, we present the realization of SECS-I, SECS-II and HSMS communication protocol between factory host computer and wafer aligner. Its validity is shown in actual test environment.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.751-752
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• 2007

• 대한산업공학회지
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• 제36권1호
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• pp.42-51
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• 2010

The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.

• 유공압시스템학회논문집
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• 제8권3호
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• pp.14-20
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• 2011

This study aims at aligning multiple wafers to reduce wafer handling time in wafer processes. We designed a multilevel structure for a prealigner which can handle multiple wafer simultaneously in a system. The system consists of gripping parts, kinematic parts, vacuum chucks, pneumatic units, hall sensors and a DSP controller. Aligning procedure has two steps: mechanical gripping and notch finding. In the first step, a wafer is aligned in XY directions using 4-point mechanical contact. The rotational error can be found by detecting a signal in a notch using hall sensors. A dual prealigner was designed for 300mm wafers and constructed for a performance test. The accuracy was monitored by checking the movement of a notch in a machine vision. The result shows that the dual prealigner has enough performance as commercial products.

• 지능정보연구
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• 제15권4호
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• pp.213-224
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• 2009

본 연구는 국내 300mm 웨이퍼를 이용하여 반도체 제품의 제조라인을 대상으로 수행 되었던 자동화 생산을 위한 일정계획 시스템 재 구축 프로젝트에 관한 내용이다. 본 프로젝트의 주요 목적은 반도체 제조라인 내의 세정, 확산, 포토, 증착과 같은 주요공정들을 대상으로 효율적인 일정계획 수립 알고리듬을 개발하고 그것을 실시간 일정계획 시스템에 구현함으로써 반도체 제조라인의 자동화 생산률을 향상시키는 것이다. 본 논문에서는 여러가지 주요 공정들 중 제한된 대기시간 제약과 배치공정의 특성이 존재하는 세정과 확산으로 이루어진 연속공정 구간을 대상으로 개발된 일정계획 알고리듬과 실시간 일정계획 시스템의 개발에 대한 내용에 초점을 두었다. 일정계획 시스템 재 구축 프로젝트가 시작 될 시점에 세정과 확산 공정의 자동화 생산률은 각각 50%와 10% 정도 였으나, 프로젝트 수행 완료 후에는 각각 91%와 83% 까지 자동화 생산률이 향상 되었다. 자동화 생산률의 향상은 작업자의 인건비 절감, 생산성의 향상, 지속적이고 편차 없는 생산을 의미한다.