• Journal of Power Electronics
• /
• 제19권3호
• /
• pp.702-713
• /
• 2019

Multilevel Inverters (MLIs) are widely used in medium voltage applications due to their various advantages. In addition, there are numerous types of MLIs for such applications. However, the diode-less 3-level (3L) T-type Neutral Point Clamped (NPC) MLI is the most advantageous due to its low conduction losses and high potential efficiency. The power circuit of a 3L T-type NPC is derived by the conventional two level inverter by a slight modification. In order to explore the MLI performance for various Pulse Width Modulation (PWM) schemes, this paper examines the operation of a 3L (five level line to line) T-type NPC MLI for various types of Multi-Carriers Pulse Width Modulation (MCPWM) schemes. These PWM schemes are compared in terms of their voltage profile, total harmonic distortion (THD) and conduction losses. In addition, a 3L T-type NPC MLI is also compared with the conventional NPC in terms of number of switches, clamping diodes, main diodes and capacitors. Moreover, the capacitor-balancing problem is also investigated using the Neutral Point Fluctuation (NPF) method with all of the MCPWM schemes. A 1kW 3L T-type NPC MLI is simulated in MATLAB/Simulink and implemented experimentally and its performance is tested with a 1HP induction motor. The results indicate that the 3L T-type NPC MLI has better performance than conventional NPC MLIs.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2011년도 추계학술대회
• /
• pp.3-4
• /
• 2011

This paper presents a survey of floating power supply based on bootstrap operation for three-level voltage-source inverters. The floating power supply for upper switches is achieved by the bootstrap capacitor charged during on-time of the switch underneath. Hence, a large number of bulky isolated DC/DC power supplies for each gate driver are reduced. The Pspice simulation results show the behavior of bootstrap devices and the performance of bootstrap capacitor voltage.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2011년도 추계학술대회
• /
• pp.63-64
• /
• 2011

The inevitable calculation time delay of digital controller especially degrades the voltage control performance of three-phase UPS systems. This paper proposes time delay compensators based on the Smith-predictor for both voltage and current controllers of three-level NPC inverters. The PSIM-based simulation results show that the proposed controller with delay compensator gives improved voltage control performance with respect to time delay.

• 전력전자학회논문지
• /
• 제22권4호
• /
• pp.369-372
• /
• 2017

This paper presents a control scheme for three-level NPC inverters using small DC-link capacitors. To reduce the inverter system volume, the film capacitor with small capacitance is a promising candidate for the DC-link. When small capacitors are applied in a three level inverter, however, the AC ripple component increases in the DC-link NPV (neutral point voltage). In addition, the three-phase input grid currents are distorted when the DC-link capacitors are fed by diode rectifier. In this paper, the additional circuit is applied to compensate for small capacitor systems defect, and the offset voltage injection method is presented for the stabilization in NPV. These two proposed processes evidently ensure the quality improvement of the input grid currents and output load currents. The feasibility of the proposed method is verified by experimental results.

• 전력전자학회논문지
• /
• 제26권2호
• /
• pp.120-126
• /
• 2021

DC-link capacitors are one of the main components in two-level three-phase voltage source inverters (VSIs); they provide the pulsating input current and stabilize the vacillating DC-link voltage. Ideally, the larger the capacitance of DC-link capacitors, the better the DC-link voltage stabilizes. However, high capacitance increases the cost and decreases the power density of VSI systems. Therefore, the capacitance should be chosen carefully on the basis of the DC-link voltage ripple requirement. However, the DC-link voltage ripple is dependent on the pulse-width modulation (PWM) strategy. This study especially presents a DC-link voltage ripple analysis when the minimum loss discontinuous PWM strategy is applied. Furthermore, an equation for the selection of the minimum capacitance of DC-link capacitors is proposed. Experimental results with R-L loads are also provided to verify the effectiveness of the presented analysis.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제54권5호
• /
• pp.231-237
• /
• 2005

Many conventional multi-level inverters have detected switching faults by using the over voltage and current. However, fault detection of the switching elements is very difficult because the voltage and current due to each switching fault decrease more than the normal operation. Moreover, the dc-link unbalancing voltage causes a serious problem in the safety and reliability of system when the 3-level inverter faults occur Therefore, this paper proposes the simple fault diagnose method and the neutral-point-voltage control method that can protect the 3-level inverter system from the unbalancing voltage of the do-link capacitors when the faults of switching elements occur in the 3-level inverter that is very efficient in ac motor drives of the high voltage and high power applications. Through experiment results, the validity of the proposed method is demonstrated.

• 수산해양기술연구
• /
• 제60권1호
• /
• pp.71-79
• /
• 2024

In compliance with environmental regulations at sea and the introduction of unmanned autonomous ships, electric propulsion ships are garnering significant attention. Induction machines used as propulsion electric motor (PEM) have maintenance advantages, but speed control is very complicated and difficult. One of the most commonly used techniques for speed control is DTC (direct torque control). DTC is simple in the reference frame transformation and the stator flux calculation. Meanwhile, two-level and three-level voltage source inverters (VSI) are predominantly used. The three-level VSI has more flexibility in voltage space vector selection compared to the two-level VSI. In this paper, speed is controlled using the DTC method based on the specifications of the PEM. The speed controller employs a PI controller with anti-windup functionality. In addition, the characteristics of the two-level VSI and three-level VSI are compared under identical conditions. It was confirmed through simulation that proper control of speed and torque has been achieved. In particular, the torque ripple was small and control was possible with a low DC voltage at low speed in the three-level VSI. The study confirmed that the application of DTC, using a three-level VSI, contributes to enhancing the system's response performance.

• Journal of Power Electronics
• /
• 제18권3호
• /
• pp.863-870
• /
• 2018

The traditional power control theories for the harmonic reduction methods in multilevel inverters are found to be unreliable under unbalanced load conditions. The unreliability in harmonic mitigation is caused by voltage fluctuations, non-linear loads, the use of power switches, etc. In general, the harmonics are reduced by filters. However, such devices are an expensive way to provide a smooth and fast response to secure power systems during dynamic conditions. Hence, the Decoupled Double Synchronous Reference Frame (DDSRF) theory combined with a State Delay Controller (SDC) is proposed to achieve a harmonic reduction in power systems. The DDSRF produces a sinusoidal harmonic that is the opposite of the load harmonic. Then, it injects this harmonic into power systems, which reduces the effect of harmonics. The SDC is used to reduce the delay between the compensation time for power injection and the generation of a reference signal. The proposed technique has been simulated using MATLAB and its reliability has been verified experimentally under unbalanced conditions.

• Journal of Power Electronics
• /
• 제3권2호
• /
• pp.90-98
• /
• 2003

This paper presents a performance analysis in steady-state of a novel type Auxiliary Resonant Commutation Snubber-linked 3-level 3-phase voltage source soft switching inverter suitable and acceptable for high-power applications in comparison with other three types of 3-level 3-phase voltage source soft switching inverters. This soft switching inverter operation which can operate under a condition of Zero Voltage Switching (ZVS). The practical steady -state performances of this inverter are illustrated and evaluated on the basis of the experimental results.

• 전력전자학회논문지
• /
• 제11권2호
• /
• pp.135-141
• /
• 2006

본 논문은 단상 멀티레벨 인버터의 LC출력 필터 설계와 변조비에 따른 고조파 분석을 수행하였다. 일반적으로 고전력 응용에 적합한 멀티레벨 인버터는 낮은 스위칭 주파수하에서 구동되므로 출력단에 큰 고조파 성분을 포함하게 된다. 이를 감소시키기 위해 출력단에 필터를 삽입하는 방법이 효과적이다. 3레벨 NPC 멀티레벨 인버터의 출력단 고조파를 감소시키기 위한 필터 설계 방안을 검토하고, 디지털 제어 방식을 위해 DSP(TMS320C31)를 사용하였다. 또한 필터의 설계예시를 보였고, 설계된 시스템의 타당성을 시뮬레이션과 실험을 통해 입증하였다.