• Journal of Power Electronics
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• 제11권5호
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• pp.688-696
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• 2011

This paper proposes a simple space vector PWM (SVPWM) scheme including overmodulation operation for 3-level NPC (Neutral Point Clamped) Inverters. The proposed scheme features a simple decision and calculation procedure for determining switching times in the overmodulation range by utilizing the duty calculation method used in 2-level inverters and the minimum phase error projection method widely employed in motor drive systems. The proposed scheme does not need to detect the angle of the reference vector or calculate trigonometric functions to determine the magnitude of the voltage vector. The magnitude of the angle of the new reference voltage vector is decided in advance with the help of the Fourier Series Expansion to extend the linearity of the output voltage of 3-level inverters in the overmodulation region. Experimental results demonstrate the validity of the proposed SVPWM scheme including overmodulation operation for 3-level NPC inverters.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.487-488
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• 2016

In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1203-1210
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• 2017

Switched-inductor (SL) Z-source three-level inverter is a novel high power topology. The SL based impedance network can boost the input dc voltage to a higher value than the single LC impedance network. However, as all the neutral-point-clamped (NPC) inverters, the SL Z-source three-level inverter has to balance the neutral-point (NP) potential too. The principle of the inverter is introduced and then the effects of NP potential unbalance are analyzed. A NP balancing method is proposed. Other than the methods for conventional NPC inverter without Z-source impedance network, the upper and lower shoot-through durations are corrected by the feedforward compensation factors. With the proposed method, the NP potential is balanced and the voltage boosting ability of the Z-source network is not affected obviously. Simulations are conducted to verify the proposed method.

• Journal of Power Electronics
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• 제16권2호
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• pp.455-463
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• 2016

This paper proposes a compensation method to improve the distorted space vectors when a 3-level Neutral Point Clamped (NPC) inverter has an unbalanced neutral point voltage. Since both the neutral point voltage of the DC link and the space vector of a 3-level NPC inverter are closely related depending on the output load connecting state, a distorted space vector can occur when the neutral point voltage of a 3-level NPC inverter is unbalanced. The proposed method can improve the distorted space vectors by adjusting the injection time of the small and medium vectors and by modulating the amplitude of the carrier waveforms. In this paper, the proposed method is verified by both simulation and experimental results based on a 3-level NPC inverter.

• Journal of Power Electronics
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• 제19권3호
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• pp.702-713
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• 2019

Multilevel Inverters (MLIs) are widely used in medium voltage applications due to their various advantages. In addition, there are numerous types of MLIs for such applications. However, the diode-less 3-level (3L) T-type Neutral Point Clamped (NPC) MLI is the most advantageous due to its low conduction losses and high potential efficiency. The power circuit of a 3L T-type NPC is derived by the conventional two level inverter by a slight modification. In order to explore the MLI performance for various Pulse Width Modulation (PWM) schemes, this paper examines the operation of a 3L (five level line to line) T-type NPC MLI for various types of Multi-Carriers Pulse Width Modulation (MCPWM) schemes. These PWM schemes are compared in terms of their voltage profile, total harmonic distortion (THD) and conduction losses. In addition, a 3L T-type NPC MLI is also compared with the conventional NPC in terms of number of switches, clamping diodes, main diodes and capacitors. Moreover, the capacitor-balancing problem is also investigated using the Neutral Point Fluctuation (NPF) method with all of the MCPWM schemes. A 1kW 3L T-type NPC MLI is simulated in MATLAB/Simulink and implemented experimentally and its performance is tested with a 1HP induction motor. The results indicate that the 3L T-type NPC MLI has better performance than conventional NPC MLIs.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2010년도 하계학술대회 논문집
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• pp.434-435
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• 2010

본 논문에서는 배전급 고전압(1kV~7.2kV) 계통 연계가 가능한 새로운 3 병렬 3 레벨 NPC(Neutral-Point-Clamped) 컨버터/인버터 회로방식을 제안한다. 이 회로방식은 정격 용량의 1/3 크기를 가지는 NPC 컨버터/인버터 모듈을 3 병렬로 구성하면서 직류단 캐패시터를 병렬 연결하여 중성점 전위 변동을 저감할 수 있는 특징을 가진다. 제안된 3 병렬 3 레벨 NPC 컨버터/인버터는 기존의 NPC 컨버터의 장점을 가지면서 동시에 용량 확장이 가능하고, 하나의 모듈이 고장 상태가 되더라도 부분 운전이 가능하여 시스템의 신뢰성을 증대시킬 수 있다. 본 논문에서는 제안된 중성점 전압 제어 전략을 실험을 통하여 검증한다. 정밀한 중성점 전압 제어를 위한 중성점 전류 제어 방법이 3병렬 구조에서 안정적으로 동작함을 컴퓨터 모의 실험을 통해 검증한다.

• 전력전자학회논문지
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• 제19권2호
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• pp.173-183
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• 2014

In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.

• 전력전자학회논문지
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• 제22권4호
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• pp.369-372
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• 2017

This paper presents a control scheme for three-level NPC inverters using small DC-link capacitors. To reduce the inverter system volume, the film capacitor with small capacitance is a promising candidate for the DC-link. When small capacitors are applied in a three level inverter, however, the AC ripple component increases in the DC-link NPV (neutral point voltage). In addition, the three-phase input grid currents are distorted when the DC-link capacitors are fed by diode rectifier. In this paper, the additional circuit is applied to compensate for small capacitor systems defect, and the offset voltage injection method is presented for the stabilization in NPV. These two proposed processes evidently ensure the quality improvement of the input grid currents and output load currents. The feasibility of the proposed method is verified by experimental results.

• 전력전자학회논문지
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• 제24권6호
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• pp.459-462
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• 2019

This work presents methods for reducing overshoot voltages across the drain-source of silicon carbide (SiC) MOSFETs in grid-connected hybrid active neutral-point-clamped (ANPC) inverters. Compared with 3-level NPC-type inverter, the hybrid ANPC inverter can realize the high efficiency. However, SiC MOSFETs conduct its switching operation at high frequencies, which cause high overshoot voltages in such devices. These overshoot voltages should be reduced because they may damage switching devices and result in electromagnetic interference (EMI). Two major strategies are used to reduce the overshoot voltages, namely, adjusting the gate resistor and using a snubber capacitor. In this paper, advantages and disadvantages of these methods will be discussed. The effectiveness of these strategies is verified by experimental results.

• Journal of Power Electronics
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• 제18권3호
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• pp.702-713
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• 2018

Power loss reduction and total harmonic distortion(THD) minimization are two important goals of improving three-level inverters. In this paper, an optimized pulse width modulation (PWM) strategy that can reduce switching losses and balance the neutral point with an optional THD of three-level neutral-point-clamped inverters is proposed. An analysis of the two-level discontinuous PWM (DPWM) strategy indicates that the optimal goal of the proposed PWM strategy is to reduce switching losses to a minimum without increasing the THD compared to that of traditional SVPWMs. Thus, the analysis of the two-level DPWM strategy is introduced. Through the rational allocation of the zero vector, only two-phase switching devices are active in each sector, and their switching losses can be reduced by one-third compared with those of traditional PWM strategies. A detailed analysis of the impact of small vectors, which correspond to different zero vectors, on the neutral-point potential is conducted, and a hysteresis control method is proposed to balance the neutral point. This method is simple, does not judge the direction of midpoint currents, and can adjust the switching times of devices and the fluctuation of the neutral-point potential by changing the hysteresis loop width. Simulation and experimental results prove the effectiveness and feasibility of the proposed strategy.